77853b9f52
Any change of control flow now resets the itstate to 0 mask and 0 condition, except where the control flow alteration write into the cpsr register. These case, for example return from an iterrupt, require the predecoder to recover the itstate. As there is a window of opportunity between the return from an interrupt changing the control flow at the head of the pipe and the commit of the update to the CPSR, the predecoder needs to be able to grab the ITstate early. This is now handled by setting the forcedItState inside a PCstate for the control flow altering instruction. That instruction will have the correct mask/cond, but will not have a valid itstate until advancePC is called (note this happens to advance the execution). When the new PCstate is copy constructed it gets the itstate cond/mask, and upon advancing the PC the itstate becomes valid. Subsequent advancing invalidates the state and zeroes the cond/mask. This is handled in isolation for the ARM ISA and should have no impact on other ISAs. Refer arch/arm/types.hh and arch/arm/predecoder.cc for the details.
369 lines
15 KiB
C++
369 lines
15 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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header_output = ""
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decoder_output = ""
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exec_output = ""
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class LoadInst(LoadStoreInst):
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execBase = 'Load'
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def __init__(self, mnem, post, add, writeback,
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size=4, sign=False, user=False, flavor="normal"):
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super(LoadInst, self).__init__()
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self.name = mnem
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self.post = post
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self.add = add
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self.writeback = writeback
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self.size = size
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self.sign = sign
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self.user = user
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self.flavor = flavor
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if self.add:
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self.op = " +"
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else:
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self.op = " -"
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self.memFlags = ["ArmISA::TLB::MustBeOne"]
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self.codeBlobs = {"postacc_code" : ""}
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def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
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global header_output, decoder_output, exec_output
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codeBlobs = self.codeBlobs
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codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
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(newHeader,
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newDecoder,
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newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
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self.memFlags, instFlags, base, wbDecl)
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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class RfeInst(LoadInst):
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decConstBase = 'Rfe'
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def __init__(self, mnem, post, add, writeback):
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super(RfeInst, self).__init__(mnem, post, add, writeback)
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self.Name = "RFE_" + loadImmClassName(post, add, writeback, 8)
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self.memFlags.append("ArmISA::TLB::AlignWord")
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def emit(self):
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offset = 0
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if self.post != self.add:
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offset += 4
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if not self.add:
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offset -= 8
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self.codeBlobs["ea_code"] = "EA = Base + %d;" % offset
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wbDiff = -8
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if self.add:
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wbDiff = 8
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accCode = '''
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CPSR cpsr = Cpsr;
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SCTLR sctlr = Sctlr;
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// Use the version of NPC that gets set before NextThumb
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pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
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uint32_t tempSpsr = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
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uint32_t newCpsr =
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cpsrWriteByInstr(cpsr | CondCodes, tempSpsr,
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0xF, true, sctlr.nmfi);
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Cpsr = ~CondCodesMask & newCpsr;
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NextThumb = ((CPSR)newCpsr).t;
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NextJazelle = ((CPSR)newCpsr).j;
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ForcedItState = ((((CPSR)tempSpsr).it2 << 2) & 0xFC)
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| (((CPSR)tempSpsr).it1 & 0x3);
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CondCodes = CondCodesMask & newCpsr;
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'''
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self.codeBlobs["memacc_code"] = accCode
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wbDecl = None
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if self.writeback:
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wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
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self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
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class LoadImmInst(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadImmInst, self).__init__(*args, **kargs)
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self.offset = self.op + " imm"
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if self.add:
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self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
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else:
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self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
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class LoadRegInst(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadRegInst, self).__init__(*args, **kargs)
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self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
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" shiftType, CondCodes<29:>)"
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if self.add:
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self.wbDecl = '''
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MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
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'''
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else:
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self.wbDecl = '''
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MicroSubUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
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'''
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class LoadSingle(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadSingle, self).__init__(*args, **kargs)
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# Build the default class name
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self.Name = self.nameFunc(self.post, self.add, self.writeback,
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self.size, self.sign, self.user)
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# Add memory request flags where necessary
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self.memFlags.append("%d" % (self.size - 1))
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if self.user:
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self.memFlags.append("ArmISA::TLB::UserMode")
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self.instFlags = []
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if self.flavor == "dprefetch":
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self.memFlags.append("Request::PREFETCH")
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self.instFlags = ['IsDataPrefetch']
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elif self.flavor == "iprefetch":
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self.memFlags.append("Request::PREFETCH")
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self.instFlags = ['IsInstPrefetch']
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elif self.flavor == "exclusive":
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self.memFlags.append("Request::LLSC")
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elif self.flavor == "normal":
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self.memFlags.append("ArmISA::TLB::AllowUnaligned")
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# Disambiguate the class name for different flavors of loads
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if self.flavor != "normal":
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self.Name = "%s_%s" % (self.name.upper(), self.Name)
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def emit(self):
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# Address compuation code
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eaCode = "EA = Base"
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if not self.post:
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eaCode += self.offset
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eaCode += ";"
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if self.flavor == "fp":
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eaCode += vfpEnabledCheckCode
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self.codeBlobs["ea_code"] = eaCode
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# Code that actually handles the access
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if self.flavor == "dprefetch" or self.flavor == "iprefetch":
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accCode = 'uint64_t temp = Mem%s; temp = temp;'
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elif self.flavor == "fp":
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accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
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else:
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accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
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accCode = accCode % buildMemSuffix(self.sign, self.size)
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self.codeBlobs["memacc_code"] = accCode
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# Push it out to the output files
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base = buildMemBase(self.basePrefix, self.post, self.writeback)
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wbDecl = None
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if self.writeback:
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wbDecl = self.wbDecl
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self.emitHelper(base, wbDecl, self.instFlags)
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def loadImmClassName(post, add, writeback, size=4, sign=False, user=False):
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return memClassName("LOAD_IMM", post, add, writeback, size, sign, user)
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class LoadImm(LoadImmInst, LoadSingle):
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decConstBase = 'LoadImm'
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basePrefix = 'MemoryImm'
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nameFunc = staticmethod(loadImmClassName)
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def loadRegClassName(post, add, writeback, size=4, sign=False, user=False):
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return memClassName("LOAD_REG", post, add, writeback, size, sign, user)
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class LoadReg(LoadRegInst, LoadSingle):
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decConstBase = 'LoadReg'
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basePrefix = 'MemoryReg'
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nameFunc = staticmethod(loadRegClassName)
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class LoadDouble(LoadInst):
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def __init__(self, *args, **kargs):
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super(LoadDouble, self).__init__(*args, **kargs)
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# Build the default class name
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self.Name = self.nameFunc(self.post, self.add, self.writeback)
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# Add memory request flags where necessary
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if self.flavor == "exclusive":
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self.memFlags.append("Request::LLSC")
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self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
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else:
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self.memFlags.append("ArmISA::TLB::AlignWord")
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# Disambiguate the class name for different flavors of loads
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if self.flavor != "normal":
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self.Name = "%s_%s" % (self.name.upper(), self.Name)
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def emit(self):
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# Address computation code
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eaCode = "EA = Base"
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if not self.post:
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eaCode += self.offset
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eaCode += ";"
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if self.flavor == "fp":
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eaCode += vfpEnabledCheckCode
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self.codeBlobs["ea_code"] = eaCode
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# Code that actually handles the access
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if self.flavor != "fp":
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accCode = '''
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CPSR cpsr = Cpsr;
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Dest = cSwap<uint32_t>(Mem.ud, cpsr.e);
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Dest2 = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
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'''
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else:
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accCode = '''
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uint64_t swappedMem = cSwap(Mem.ud, ((CPSR)Cpsr).e);
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FpDest.uw = (uint32_t)swappedMem;
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FpDest2.uw = (uint32_t)(swappedMem >> 32);
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'''
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self.codeBlobs["memacc_code"] = accCode
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# Push it out to the output files
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base = buildMemBase(self.basePrefix, self.post, self.writeback)
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wbDecl = None
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if self.writeback:
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wbDecl = self.wbDecl
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self.emitHelper(base, wbDecl)
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def loadDoubleImmClassName(post, add, writeback):
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return memClassName("LOAD_IMMD", post, add, writeback, 4, False, False)
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class LoadDoubleImm(LoadImmInst, LoadDouble):
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decConstBase = 'LoadStoreDImm'
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basePrefix = 'MemoryDImm'
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nameFunc = staticmethod(loadDoubleImmClassName)
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def loadDoubleRegClassName(post, add, writeback):
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return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
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class LoadDoubleReg(LoadRegInst, LoadDouble):
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decConstBase = 'LoadDReg'
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basePrefix = 'MemoryDReg'
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nameFunc = staticmethod(loadDoubleRegClassName)
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def buildLoads(mnem, size=4, sign=False, user=False):
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LoadImm(mnem, True, True, True, size, sign, user).emit()
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LoadReg(mnem, True, True, True, size, sign, user).emit()
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LoadImm(mnem, True, False, True, size, sign, user).emit()
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LoadReg(mnem, True, False, True, size, sign, user).emit()
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LoadImm(mnem, False, True, True, size, sign, user).emit()
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LoadReg(mnem, False, True, True, size, sign, user).emit()
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LoadImm(mnem, False, False, True, size, sign, user).emit()
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LoadReg(mnem, False, False, True, size, sign, user).emit()
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LoadImm(mnem, False, True, False, size, sign, user).emit()
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LoadReg(mnem, False, True, False, size, sign, user).emit()
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LoadImm(mnem, False, False, False, size, sign, user).emit()
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LoadReg(mnem, False, False, False, size, sign, user).emit()
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def buildDoubleLoads(mnem):
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LoadDoubleImm(mnem, True, True, True).emit()
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LoadDoubleReg(mnem, True, True, True).emit()
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LoadDoubleImm(mnem, True, False, True).emit()
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LoadDoubleReg(mnem, True, False, True).emit()
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LoadDoubleImm(mnem, False, True, True).emit()
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LoadDoubleReg(mnem, False, True, True).emit()
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LoadDoubleImm(mnem, False, False, True).emit()
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LoadDoubleReg(mnem, False, False, True).emit()
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LoadDoubleImm(mnem, False, True, False).emit()
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LoadDoubleReg(mnem, False, True, False).emit()
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LoadDoubleImm(mnem, False, False, False).emit()
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LoadDoubleReg(mnem, False, False, False).emit()
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def buildRfeLoads(mnem):
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RfeInst(mnem, True, True, True).emit()
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RfeInst(mnem, True, True, False).emit()
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RfeInst(mnem, True, False, True).emit()
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RfeInst(mnem, True, False, False).emit()
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RfeInst(mnem, False, True, True).emit()
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RfeInst(mnem, False, True, False).emit()
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RfeInst(mnem, False, False, True).emit()
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RfeInst(mnem, False, False, False).emit()
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def buildPrefetches(mnem, type):
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LoadReg(mnem, False, False, False, size=1, flavor=type).emit()
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LoadImm(mnem, False, False, False, size=1, flavor=type).emit()
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LoadReg(mnem, False, True, False, size=1, flavor=type).emit()
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LoadImm(mnem, False, True, False, size=1, flavor=type).emit()
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buildLoads("ldr")
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buildLoads("ldrt", user=True)
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buildLoads("ldrb", size=1)
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buildLoads("ldrbt", size=1, user=True)
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buildLoads("ldrsb", size=1, sign=True)
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buildLoads("ldrsbt", size=1, sign=True, user=True)
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buildLoads("ldrh", size=2)
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buildLoads("ldrht", size=2, user=True)
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buildLoads("hdrsh", size=2, sign=True)
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buildLoads("ldrsht", size=2, sign=True, user=True)
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buildDoubleLoads("ldrd")
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buildRfeLoads("rfe")
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buildPrefetches("pld", "dprefetch")
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buildPrefetches("pldw", "dprefetch")
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buildPrefetches("pli", "iprefetch")
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LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit()
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LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit()
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LoadImm("ldrexb", False, True, False, size=1, flavor="exclusive").emit()
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LoadDoubleImm("ldrexd", False, True, False, flavor="exclusive").emit()
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LoadImm("vldr", False, True, False, size=4, flavor="fp").emit()
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LoadImm("vldr", False, False, False, size=4, flavor="fp").emit()
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LoadDoubleImm("vldr", False, True, False, flavor="fp").emit()
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LoadDoubleImm("vldr", False, False, False, flavor="fp").emit()
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}};
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