771c864bf4
For systems with a tightly coupled L2, a stride-based prefetcher may observe access requests from both instruction and data L1 caches. However, the PC address of an instruction miss gives no relevant training information to the stride based prefetcher(there is no stride to train). In theses cases, its better if the L2 stride prefetcher simply reverted back to a simple N-block ahead prefetcher. This patch enables this option. Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
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| .. | ||
| prefetch | ||
| tags | ||
| base.cc | ||
| base.hh | ||
| BaseCache.py | ||
| blk.cc | ||
| blk.hh | ||
| cache.cc | ||
| cache.hh | ||
| cache_impl.hh | ||
| mshr.cc | ||
| mshr.hh | ||
| mshr_queue.cc | ||
| mshr_queue.hh | ||
| SConscript | ||