76cd4393c0
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically: * Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section. * Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects. * Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections). * The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects. * Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
745 lines
23 KiB
C++
745 lines
23 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* Copyright (c) 2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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* Rick Strong
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*/
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#include <iostream>
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#include <sstream>
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#include <string>
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#include "arch/tlb.hh"
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#include "base/loader/symtab.hh"
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#include "base/cprintf.hh"
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/base.hh"
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#include "cpu/cpuevent.hh"
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#include "cpu/profile.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Mwait.hh"
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#include "debug/SyscallVerbose.hh"
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#include "mem/page_table.hh"
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#include "params/BaseCPU.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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// Hack
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#include "sim/stat_control.hh"
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using namespace std;
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vector<BaseCPU *> BaseCPU::cpuList;
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// This variable reflects the max number of threads in any CPU. Be
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// careful to only use it once all the CPUs that you care about have
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// been initialized
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int maxThreadsPerCPU = 1;
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CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
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: Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
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cpu(_cpu), _repeatEvent(true)
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{
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if (_interval)
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cpu->schedule(this, curTick() + _interval);
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}
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void
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CPUProgressEvent::process()
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{
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Counter temp = cpu->totalOps();
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if (_repeatEvent)
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cpu->schedule(this, curTick() + _interval);
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if(cpu->switchedOut()) {
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return;
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}
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#ifndef NDEBUG
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double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
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DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
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"%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
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ipc);
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ipc = 0.0;
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#else
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cprintf("%lli: %s progress event, total committed:%i, progress insts "
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"committed: %lli\n", curTick(), cpu->name(), temp,
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temp - lastNumInst);
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#endif
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lastNumInst = temp;
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}
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const char *
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CPUProgressEvent::description() const
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{
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return "CPU Progress";
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}
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BaseCPU::BaseCPU(Params *p, bool is_checker)
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: MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
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_instMasterId(p->system->getMasterId(name() + ".inst")),
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_dataMasterId(p->system->getMasterId(name() + ".data")),
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_taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
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_switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()),
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interrupts(p->interrupts), profileEvent(NULL),
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numThreads(p->numThreads), system(p->system),
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functionTraceStream(nullptr), currentFunctionStart(0),
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currentFunctionEnd(0), functionEntryTick(0),
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addressMonitor()
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{
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// if Python did not provide a valid ID, do it here
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if (_cpuId == -1 ) {
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_cpuId = cpuList.size();
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}
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// add self to global list of CPUs
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cpuList.push_back(this);
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DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n",
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_cpuId, _socketId);
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if (numThreads > maxThreadsPerCPU)
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maxThreadsPerCPU = numThreads;
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// allocate per-thread instruction-based event queues
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comInstEventQueue = new EventQueue *[numThreads];
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for (ThreadID tid = 0; tid < numThreads; ++tid)
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comInstEventQueue[tid] =
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new EventQueue("instruction-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_insts_any_thread != 0) {
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const char *cause = "a thread reached the max instruction count";
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for (ThreadID tid = 0; tid < numThreads; ++tid)
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scheduleInstStop(tid, p->max_insts_any_thread, cause);
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}
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// Set up instruction-count-based termination events for SimPoints
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// Typically, there are more than one action points.
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// Simulation.py is responsible to take the necessary actions upon
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// exitting the simulation loop.
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if (!p->simpoint_start_insts.empty()) {
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const char *cause = "simpoint starting point found";
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for (size_t i = 0; i < p->simpoint_start_insts.size(); ++i)
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scheduleInstStop(0, p->simpoint_start_insts[i], cause);
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}
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if (p->max_insts_all_threads != 0) {
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const char *cause = "all threads reached the max instruction count";
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = numThreads;
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new CountedExitEvent(cause, *counter);
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comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
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}
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}
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// allocate per-thread load-based event queues
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comLoadEventQueue = new EventQueue *[numThreads];
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for (ThreadID tid = 0; tid < numThreads; ++tid)
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comLoadEventQueue[tid] = new EventQueue("load-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_loads_any_thread != 0) {
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const char *cause = "a thread reached the max load count";
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for (ThreadID tid = 0; tid < numThreads; ++tid)
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scheduleLoadStop(tid, p->max_loads_any_thread, cause);
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}
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if (p->max_loads_all_threads != 0) {
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const char *cause = "all threads reached the max load count";
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = numThreads;
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new CountedExitEvent(cause, *counter);
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comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
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}
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}
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functionTracingEnabled = false;
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if (p->function_trace) {
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const string fname = csprintf("ftrace.%s", name());
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functionTraceStream = simout.find(fname);
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if (!functionTraceStream)
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functionTraceStream = simout.create(fname);
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currentFunctionStart = currentFunctionEnd = 0;
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functionEntryTick = p->function_trace_start;
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if (p->function_trace_start == 0) {
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functionTracingEnabled = true;
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} else {
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typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
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Event *event = new wrap(this, true);
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schedule(event, p->function_trace_start);
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}
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}
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// The interrupts should always be present unless this CPU is
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// switched in later or in case it is a checker CPU
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if (!params()->switched_out && !is_checker) {
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if (interrupts) {
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interrupts->setCPU(this);
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} else {
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fatal("CPU %s has no interrupt controller.\n"
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"Ensure createInterruptController() is called.\n", name());
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}
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}
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if (FullSystem) {
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if (params()->profile)
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profileEvent = new ProfileEvent(this, params()->profile);
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}
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tracer = params()->tracer;
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if (params()->isa.size() != numThreads) {
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fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
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"of threads (%i).\n", params()->isa.size(), numThreads);
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}
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}
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void
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BaseCPU::enableFunctionTrace()
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{
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functionTracingEnabled = true;
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}
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BaseCPU::~BaseCPU()
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{
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delete profileEvent;
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delete[] comLoadEventQueue;
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delete[] comInstEventQueue;
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}
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void
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BaseCPU::armMonitor(Addr address)
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{
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addressMonitor.armed = true;
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addressMonitor.vAddr = address;
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addressMonitor.pAddr = 0x0;
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DPRINTF(Mwait,"Armed monitor (vAddr=0x%lx)\n", address);
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}
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bool
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BaseCPU::mwait(PacketPtr pkt)
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{
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if(addressMonitor.gotWakeup == false) {
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int block_size = cacheLineSize();
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uint64_t mask = ~((uint64_t)(block_size - 1));
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assert(pkt->req->hasPaddr());
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addressMonitor.pAddr = pkt->getAddr() & mask;
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addressMonitor.waiting = true;
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DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
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addressMonitor.vAddr, addressMonitor.pAddr);
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return true;
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} else {
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addressMonitor.gotWakeup = false;
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return false;
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}
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}
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void
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BaseCPU::mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb)
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{
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Request req;
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Addr addr = addressMonitor.vAddr;
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int block_size = cacheLineSize();
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uint64_t mask = ~((uint64_t)(block_size - 1));
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int size = block_size;
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//The address of the next line if it crosses a cache line boundary.
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Addr secondAddr = roundDown(addr + size - 1, block_size);
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if (secondAddr > addr)
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size = secondAddr - addr;
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req.setVirt(0, addr, size, 0x0, dataMasterId(), tc->instAddr());
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// translate to physical address
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Fault fault = dtb->translateAtomic(&req, tc, BaseTLB::Read);
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assert(fault == NoFault);
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addressMonitor.pAddr = req.getPaddr() & mask;
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addressMonitor.waiting = true;
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DPRINTF(Mwait,"mwait called (vAddr=0x%lx, line's paddr=0x%lx)\n",
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addressMonitor.vAddr, addressMonitor.pAddr);
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}
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void
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BaseCPU::init()
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{
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if (!params()->switched_out) {
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registerThreadContexts();
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verifyMemoryMode();
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}
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}
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void
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BaseCPU::startup()
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{
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if (FullSystem) {
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if (!params()->switched_out && profileEvent)
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schedule(profileEvent, curTick());
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}
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if (params()->progress_interval) {
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new CPUProgressEvent(this, params()->progress_interval);
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}
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}
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ProbePoints::PMUUPtr
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BaseCPU::pmuProbePoint(const char *name)
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{
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ProbePoints::PMUUPtr ptr;
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ptr.reset(new ProbePoints::PMU(getProbeManager(), name));
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return ptr;
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}
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void
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BaseCPU::regProbePoints()
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{
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ppCycles = pmuProbePoint("Cycles");
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ppRetiredInsts = pmuProbePoint("RetiredInsts");
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ppRetiredLoads = pmuProbePoint("RetiredLoads");
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ppRetiredStores = pmuProbePoint("RetiredStores");
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ppRetiredBranches = pmuProbePoint("RetiredBranches");
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}
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void
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BaseCPU::probeInstCommit(const StaticInstPtr &inst)
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{
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if (!inst->isMicroop() || inst->isLastMicroop())
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ppRetiredInsts->notify(1);
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if (inst->isLoad())
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ppRetiredLoads->notify(1);
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if (inst->isStore())
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ppRetiredStores->notify(1);
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if (inst->isControl())
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ppRetiredBranches->notify(1);
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}
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void
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BaseCPU::regStats()
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{
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using namespace Stats;
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numCycles
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.name(name() + ".numCycles")
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.desc("number of cpu cycles simulated")
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;
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numWorkItemsStarted
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.name(name() + ".numWorkItemsStarted")
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.desc("number of work items this cpu started")
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;
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numWorkItemsCompleted
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.name(name() + ".numWorkItemsCompleted")
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.desc("number of work items this cpu completed")
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;
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int size = threadContexts.size();
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if (size > 1) {
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for (int i = 0; i < size; ++i) {
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stringstream namestr;
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ccprintf(namestr, "%s.ctx%d", name(), i);
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threadContexts[i]->regStats(namestr.str());
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}
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} else if (size == 1)
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threadContexts[0]->regStats(name());
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}
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BaseMasterPort &
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BaseCPU::getMasterPort(const string &if_name, PortID idx)
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{
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// Get the right port based on name. This applies to all the
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// subclasses of the base CPU and relies on their implementation
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// of getDataPort and getInstPort. In all cases there methods
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// return a MasterPort pointer.
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if (if_name == "dcache_port")
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return getDataPort();
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else if (if_name == "icache_port")
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return getInstPort();
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else
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return MemObject::getMasterPort(if_name, idx);
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}
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void
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BaseCPU::registerThreadContexts()
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{
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ThreadID size = threadContexts.size();
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for (ThreadID tid = 0; tid < size; ++tid) {
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ThreadContext *tc = threadContexts[tid];
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/** This is so that contextId and cpuId match where there is a
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* 1cpu:1context relationship. Otherwise, the order of registration
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* could affect the assignment and cpu 1 could have context id 3, for
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* example. We may even want to do something like this for SMT so that
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* cpu 0 has the lowest thread contexts and cpu N has the highest, but
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* I'll just do this for now
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*/
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if (numThreads == 1)
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tc->setContextId(system->registerThreadContext(tc, _cpuId));
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else
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tc->setContextId(system->registerThreadContext(tc));
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if (!FullSystem)
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tc->getProcessPtr()->assignThreadContext(tc->contextId());
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}
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}
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int
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BaseCPU::findContext(ThreadContext *tc)
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{
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ThreadID size = threadContexts.size();
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for (ThreadID tid = 0; tid < size; ++tid) {
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if (tc == threadContexts[tid])
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return tid;
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}
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return 0;
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}
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void
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BaseCPU::switchOut()
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{
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assert(!_switchedOut);
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_switchedOut = true;
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if (profileEvent && profileEvent->scheduled())
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deschedule(profileEvent);
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// Flush all TLBs in the CPU to avoid having stale translations if
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// it gets switched in later.
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flushTLBs();
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}
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void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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assert(threadContexts.size() == oldCPU->threadContexts.size());
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assert(_cpuId == oldCPU->cpuId());
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assert(_switchedOut);
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assert(oldCPU != this);
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_pid = oldCPU->getPid();
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_taskId = oldCPU->taskId();
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_switchedOut = false;
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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ThreadContext *newTC = threadContexts[i];
|
|
ThreadContext *oldTC = oldCPU->threadContexts[i];
|
|
|
|
newTC->takeOverFrom(oldTC);
|
|
|
|
CpuEvent::replaceThreadContext(oldTC, newTC);
|
|
|
|
assert(newTC->contextId() == oldTC->contextId());
|
|
assert(newTC->threadId() == oldTC->threadId());
|
|
system->replaceThreadContext(newTC, newTC->contextId());
|
|
|
|
/* This code no longer works since the zero register (e.g.,
|
|
* r31 on Alpha) doesn't necessarily contain zero at this
|
|
* point.
|
|
if (DTRACE(Context))
|
|
ThreadContext::compare(oldTC, newTC);
|
|
*/
|
|
|
|
BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
|
|
BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
|
|
BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
|
|
BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
|
|
|
|
// Move over any table walker ports if they exist
|
|
if (new_itb_port) {
|
|
assert(!new_itb_port->isConnected());
|
|
assert(old_itb_port);
|
|
assert(old_itb_port->isConnected());
|
|
BaseSlavePort &slavePort = old_itb_port->getSlavePort();
|
|
old_itb_port->unbind();
|
|
new_itb_port->bind(slavePort);
|
|
}
|
|
if (new_dtb_port) {
|
|
assert(!new_dtb_port->isConnected());
|
|
assert(old_dtb_port);
|
|
assert(old_dtb_port->isConnected());
|
|
BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
|
|
old_dtb_port->unbind();
|
|
new_dtb_port->bind(slavePort);
|
|
}
|
|
newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
|
|
newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr());
|
|
|
|
// Checker whether or not we have to transfer CheckerCPU
|
|
// objects over in the switch
|
|
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
|
|
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
|
|
if (oldChecker && newChecker) {
|
|
BaseMasterPort *old_checker_itb_port =
|
|
oldChecker->getITBPtr()->getMasterPort();
|
|
BaseMasterPort *old_checker_dtb_port =
|
|
oldChecker->getDTBPtr()->getMasterPort();
|
|
BaseMasterPort *new_checker_itb_port =
|
|
newChecker->getITBPtr()->getMasterPort();
|
|
BaseMasterPort *new_checker_dtb_port =
|
|
newChecker->getDTBPtr()->getMasterPort();
|
|
|
|
newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
|
|
newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
|
|
|
|
// Move over any table walker ports if they exist for checker
|
|
if (new_checker_itb_port) {
|
|
assert(!new_checker_itb_port->isConnected());
|
|
assert(old_checker_itb_port);
|
|
assert(old_checker_itb_port->isConnected());
|
|
BaseSlavePort &slavePort =
|
|
old_checker_itb_port->getSlavePort();
|
|
old_checker_itb_port->unbind();
|
|
new_checker_itb_port->bind(slavePort);
|
|
}
|
|
if (new_checker_dtb_port) {
|
|
assert(!new_checker_dtb_port->isConnected());
|
|
assert(old_checker_dtb_port);
|
|
assert(old_checker_dtb_port->isConnected());
|
|
BaseSlavePort &slavePort =
|
|
old_checker_dtb_port->getSlavePort();
|
|
old_checker_dtb_port->unbind();
|
|
new_checker_dtb_port->bind(slavePort);
|
|
}
|
|
}
|
|
}
|
|
|
|
interrupts = oldCPU->interrupts;
|
|
interrupts->setCPU(this);
|
|
oldCPU->interrupts = NULL;
|
|
|
|
if (FullSystem) {
|
|
for (ThreadID i = 0; i < size; ++i)
|
|
threadContexts[i]->profileClear();
|
|
|
|
if (profileEvent)
|
|
schedule(profileEvent, curTick());
|
|
}
|
|
|
|
// All CPUs have an instruction and a data port, and the new CPU's
|
|
// ports are dangling while the old CPU has its ports connected
|
|
// already. Unbind the old CPU and then bind the ports of the one
|
|
// we are switching to.
|
|
assert(!getInstPort().isConnected());
|
|
assert(oldCPU->getInstPort().isConnected());
|
|
BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
|
|
oldCPU->getInstPort().unbind();
|
|
getInstPort().bind(inst_peer_port);
|
|
|
|
assert(!getDataPort().isConnected());
|
|
assert(oldCPU->getDataPort().isConnected());
|
|
BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
|
|
oldCPU->getDataPort().unbind();
|
|
getDataPort().bind(data_peer_port);
|
|
}
|
|
|
|
void
|
|
BaseCPU::flushTLBs()
|
|
{
|
|
for (ThreadID i = 0; i < threadContexts.size(); ++i) {
|
|
ThreadContext &tc(*threadContexts[i]);
|
|
CheckerCPU *checker(tc.getCheckerCpuPtr());
|
|
|
|
tc.getITBPtr()->flushAll();
|
|
tc.getDTBPtr()->flushAll();
|
|
if (checker) {
|
|
checker->getITBPtr()->flushAll();
|
|
checker->getDTBPtr()->flushAll();
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
|
|
: cpu(_cpu), interval(_interval)
|
|
{ }
|
|
|
|
void
|
|
BaseCPU::ProfileEvent::process()
|
|
{
|
|
ThreadID size = cpu->threadContexts.size();
|
|
for (ThreadID i = 0; i < size; ++i) {
|
|
ThreadContext *tc = cpu->threadContexts[i];
|
|
tc->profileSample();
|
|
}
|
|
|
|
cpu->schedule(this, curTick() + interval);
|
|
}
|
|
|
|
void
|
|
BaseCPU::serialize(CheckpointOut &cp) const
|
|
{
|
|
SERIALIZE_SCALAR(instCnt);
|
|
|
|
if (!_switchedOut) {
|
|
/* Unlike _pid, _taskId is not serialized, as they are dynamically
|
|
* assigned unique ids that are only meaningful for the duration of
|
|
* a specific run. We will need to serialize the entire taskMap in
|
|
* system. */
|
|
SERIALIZE_SCALAR(_pid);
|
|
|
|
interrupts->serialize(cp);
|
|
|
|
// Serialize the threads, this is done by the CPU implementation.
|
|
for (ThreadID i = 0; i < numThreads; ++i) {
|
|
ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
|
|
serializeThread(cp, i);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::unserialize(CheckpointIn &cp)
|
|
{
|
|
UNSERIALIZE_SCALAR(instCnt);
|
|
|
|
if (!_switchedOut) {
|
|
UNSERIALIZE_SCALAR(_pid);
|
|
interrupts->unserialize(cp);
|
|
|
|
// Unserialize the threads, this is done by the CPU implementation.
|
|
for (ThreadID i = 0; i < numThreads; ++i) {
|
|
ScopedCheckpointSection sec(cp, csprintf("xc.%i", i));
|
|
unserializeThread(cp, i);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
|
|
{
|
|
const Tick now(comInstEventQueue[tid]->getCurTick());
|
|
Event *event(new LocalSimLoopExitEvent(cause, 0));
|
|
|
|
comInstEventQueue[tid]->schedule(event, now + insts);
|
|
}
|
|
|
|
AddressMonitor::AddressMonitor() {
|
|
armed = false;
|
|
waiting = false;
|
|
gotWakeup = false;
|
|
}
|
|
|
|
bool AddressMonitor::doMonitor(PacketPtr pkt) {
|
|
assert(pkt->req->hasPaddr());
|
|
if(armed && waiting) {
|
|
if(pAddr == pkt->getAddr()) {
|
|
DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n",
|
|
pkt->getAddr());
|
|
waiting = false;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void
|
|
BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
|
|
{
|
|
const Tick now(comLoadEventQueue[tid]->getCurTick());
|
|
Event *event(new LocalSimLoopExitEvent(cause, 0));
|
|
|
|
comLoadEventQueue[tid]->schedule(event, now + loads);
|
|
}
|
|
|
|
|
|
void
|
|
BaseCPU::traceFunctionsInternal(Addr pc)
|
|
{
|
|
if (!debugSymbolTable)
|
|
return;
|
|
|
|
// if pc enters different function, print new function symbol and
|
|
// update saved range. Otherwise do nothing.
|
|
if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
|
|
string sym_str;
|
|
bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
|
|
currentFunctionStart,
|
|
currentFunctionEnd);
|
|
|
|
if (!found) {
|
|
// no symbol found: use addr as label
|
|
sym_str = csprintf("0x%x", pc);
|
|
currentFunctionStart = pc;
|
|
currentFunctionEnd = pc + 1;
|
|
}
|
|
|
|
ccprintf(*functionTraceStream, " (%d)\n%d: %s",
|
|
curTick() - functionEntryTick, curTick(), sym_str);
|
|
functionEntryTick = curTick();
|
|
}
|
|
}
|