a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
312 lines
10 KiB
C++
312 lines
10 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_ROB_HH__
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#define __CPU_O3_ROB_HH__
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#include <string>
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#include <utility>
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#include <vector>
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/**
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* ROB class. The ROB is largely what drives squashing.
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*/
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template <class Impl>
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class ROB
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{
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protected:
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typedef TheISA::RegIndex RegIndex;
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public:
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//Typedefs from the Impl.
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
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typedef typename std::list<DynInstPtr>::iterator InstIt;
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/** Possible ROB statuses. */
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enum Status {
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Running,
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Idle,
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ROBSquashing,
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DcacheMissStall,
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DcacheMissComplete
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};
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/** SMT ROB Sharing Policy */
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enum ROBPolicy{
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Dynamic,
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Partitioned,
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Threshold
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};
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private:
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/** Per-thread ROB status. */
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Status robStatus[Impl::MaxThreads];
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/** ROB resource sharing policy for SMT mode. */
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ROBPolicy robPolicy;
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public:
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/** ROB constructor.
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* @param _numEntries Number of entries in ROB.
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* @param _squashWidth Number of instructions that can be squashed in a
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* single cycle.
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* @param _smtROBPolicy ROB Partitioning Scheme for SMT.
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* @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB.
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* @param _numThreads The number of active threads.
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*/
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ROB(unsigned _numEntries, unsigned _squashWidth, std::string smtROBPolicy,
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unsigned _smtROBThreshold, unsigned _numThreads);
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std::string name() const;
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/** Function to set the CPU pointer, necessary due to which object the ROB
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* is created within.
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* @param cpu_ptr Pointer to the implementation specific full CPU object.
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*/
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void setCPU(FullCPU *cpu_ptr);
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/** Sets pointer to the list of active threads.
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* @param at_ptr Pointer to the list of active threads.
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*/
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void setActiveThreads(std::list<unsigned>* at_ptr);
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/** Function to insert an instruction into the ROB. Note that whatever
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* calls this function must ensure that there is enough space within the
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* ROB for the new instruction.
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* @param inst The instruction being inserted into the ROB.
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*/
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void insertInst(DynInstPtr &inst);
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/** Returns pointer to the head instruction within the ROB. There is
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* no guarantee as to the return value if the ROB is empty.
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* @retval Pointer to the DynInst that is at the head of the ROB.
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*/
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DynInstPtr readHeadInst();
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/** Returns a pointer to the head instruction of a specific thread within
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* the ROB.
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* @return Pointer to the DynInst that is at the head of the ROB.
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*/
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DynInstPtr readHeadInst(unsigned tid);
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/** Returns pointer to the tail instruction within the ROB. There is
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* no guarantee as to the return value if the ROB is empty.
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* @retval Pointer to the DynInst that is at the tail of the ROB.
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*/
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DynInstPtr readTailInst();
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/** Returns a pointer to the tail instruction of a specific thread within
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* the ROB.
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* @return Pointer to the DynInst that is at the tail of the ROB.
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*/
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DynInstPtr readTailInst(unsigned tid);
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/** Retires the head instruction, removing it from the ROB. */
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void retireHead();
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/** Retires the head instruction of a specific thread, removing it from the
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* ROB.
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*/
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void retireHead(unsigned tid);
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/** Is the oldest instruction across all threads ready. */
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bool isHeadReady();
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/** Is the oldest instruction across a particular thread ready. */
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bool isHeadReady(unsigned tid);
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/** Is there any commitable head instruction across all threads ready. */
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bool canCommit();
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/** Re-adjust ROB partitioning. */
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void resetEntries();
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/** Number of entries needed For 'num_threads' amount of threads. */
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int entryAmount(int num_threads);
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/** Returns the number of total free entries in the ROB. */
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unsigned numFreeEntries();
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/** Returns the number of free entries in a specific ROB paritition. */
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unsigned numFreeEntries(unsigned tid);
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/** Returns the maximum number of entries for a specific thread. */
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unsigned getMaxEntries(unsigned tid)
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{ return maxEntries[tid]; }
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/** Returns the number of entries being used by a specific thread. */
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unsigned getThreadEntries(unsigned tid)
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{ return threadEntries[tid]; }
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/** Returns if the ROB is full. */
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bool isFull()
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{ return numInstsInROB == numEntries; }
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/** Returns if a specific thread's partition is full. */
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bool isFull(unsigned tid)
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{ return threadEntries[tid] == numEntries; }
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/** Returns if the ROB is empty. */
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bool isEmpty()
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{ return numInstsInROB == 0; }
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/** Returns if a specific thread's partition is empty. */
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bool isEmpty(unsigned tid)
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{ return threadEntries[tid] == 0; }
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/** Executes the squash, marking squashed instructions. */
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void doSquash(unsigned tid);
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/** Squashes all instructions younger than the given sequence number for
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* the specific thread.
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*/
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void squash(InstSeqNum squash_num, unsigned tid);
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/** Updates the head instruction with the new oldest instruction. */
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void updateHead();
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/** Updates the tail instruction with the new youngest instruction. */
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void updateTail();
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/** Reads the PC of the oldest head instruction. */
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uint64_t readHeadPC();
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/** Reads the PC of the head instruction of a specific thread. */
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uint64_t readHeadPC(unsigned tid);
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/** Reads the next PC of the oldest head instruction. */
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uint64_t readHeadNextPC();
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/** Reads the next PC of the head instruction of a specific thread. */
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uint64_t readHeadNextPC(unsigned tid);
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/** Reads the sequence number of the oldest head instruction. */
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InstSeqNum readHeadSeqNum();
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/** Reads the sequence number of the head instruction of a specific thread.
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*/
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InstSeqNum readHeadSeqNum(unsigned tid);
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/** Reads the PC of the youngest tail instruction. */
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uint64_t readTailPC();
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/** Reads the PC of the tail instruction of a specific thread. */
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uint64_t readTailPC(unsigned tid);
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/** Reads the sequence number of the youngest tail instruction. */
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InstSeqNum readTailSeqNum();
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/** Reads the sequence number of tail instruction of a specific thread. */
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InstSeqNum readTailSeqNum(unsigned tid);
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/** Checks if the ROB is still in the process of squashing instructions.
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* @retval Whether or not the ROB is done squashing.
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*/
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bool isDoneSquashing(unsigned tid) const
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{ return doneSquashing[tid]; }
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/** Checks if the ROB is still in the process of squashing instructions for
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* any thread.
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*/
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bool isDoneSquashing();
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/** This is more of a debugging function than anything. Use
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* numInstsInROB to get the instructions in the ROB unless you are
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* double checking that variable.
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*/
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int countInsts();
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/** This is more of a debugging function than anything. Use
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* threadEntries to get the instructions in the ROB unless you are
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* double checking that variable.
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*/
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int countInsts(unsigned tid);
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private:
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/** Pointer to the CPU. */
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FullCPU *cpu;
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/** Active Threads in CPU */
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std::list<unsigned>* activeThreads;
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/** Number of instructions in the ROB. */
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unsigned numEntries;
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/** Entries Per Thread */
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unsigned threadEntries[Impl::MaxThreads];
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/** Max Insts a Thread Can Have in the ROB */
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unsigned maxEntries[Impl::MaxThreads];
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/** ROB List of Instructions */
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std::list<DynInstPtr> instList[Impl::MaxThreads];
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/** Number of instructions that can be squashed in a single cycle. */
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unsigned squashWidth;
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public:
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/** Iterator pointing to the instruction which is the last instruction
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* in the ROB. This may at times be invalid (ie when the ROB is empty),
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* however it should never be incorrect.
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*/
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InstIt tail;
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/** Iterator pointing to the instruction which is the first instruction in
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* in the ROB*/
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InstIt head;
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private:
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/** Iterator used for walking through the list of instructions when
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* squashing. Used so that there is persistent state between cycles;
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* when squashing, the instructions are marked as squashed but not
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* immediately removed, meaning the tail iterator remains the same before
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* and after a squash.
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* This will always be set to cpu->instList.end() if it is invalid.
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*/
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InstIt squashIt[Impl::MaxThreads];
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public:
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/** Number of instructions in the ROB. */
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int numInstsInROB;
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DynInstPtr dummyInst;
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private:
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/** The sequence number of the squashed instruction. */
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InstSeqNum squashedSeqNum;
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/** Is the ROB done squashing. */
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bool doneSquashing[Impl::MaxThreads];
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/** Number of active threads. */
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unsigned numThreads;
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};
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#endif //__CPU_O3_ROB_HH__
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