a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
125 lines
4.2 KiB
C++
125 lines
4.2 KiB
C++
/*
|
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#ifndef __CPU_O3_BTB_HH__
|
|
#define __CPU_O3_BTB_HH__
|
|
|
|
// For Addr type.
|
|
#include "arch/isa_traits.hh"
|
|
|
|
class DefaultBTB
|
|
{
|
|
private:
|
|
struct BTBEntry
|
|
{
|
|
BTBEntry()
|
|
: tag(0), target(0), valid(false)
|
|
{
|
|
}
|
|
|
|
/** The entry's tag. */
|
|
Addr tag;
|
|
|
|
/** The entry's target. */
|
|
Addr target;
|
|
|
|
/** The entry's thread id. */
|
|
unsigned tid;
|
|
|
|
/** Whether or not the entry is valid. */
|
|
bool valid;
|
|
};
|
|
|
|
public:
|
|
/** Creates a BTB with the given number of entries, number of bits per
|
|
* tag, and instruction offset amount.
|
|
* @param numEntries Number of entries for the BTB.
|
|
* @param tagBits Number of bits for each tag in the BTB.
|
|
* @param instShiftAmt Offset amount for instructions to ignore alignment.
|
|
*/
|
|
DefaultBTB(unsigned numEntries, unsigned tagBits,
|
|
unsigned instShiftAmt);
|
|
|
|
/** Looks up an address in the BTB. Must call valid() first on the address.
|
|
* @param inst_PC The address of the branch to look up.
|
|
* @param tid The thread id.
|
|
* @return Returns the target of the branch.
|
|
*/
|
|
Addr lookup(const Addr &inst_PC, unsigned tid);
|
|
|
|
/** Checks if a branch is in the BTB.
|
|
* @param inst_PC The address of the branch to look up.
|
|
* @param tid The thread id.
|
|
* @return Whether or not the branch exists in the BTB.
|
|
*/
|
|
bool valid(const Addr &inst_PC, unsigned tid);
|
|
|
|
/** Updates the BTB with the target of a branch.
|
|
* @param inst_PC The address of the branch being updated.
|
|
* @param target_PC The target address of the branch.
|
|
* @param tid The thread id.
|
|
*/
|
|
void update(const Addr &inst_PC, const Addr &target_PC,
|
|
unsigned tid);
|
|
|
|
private:
|
|
/** Returns the index into the BTB, based on the branch's PC.
|
|
* @param inst_PC The branch to look up.
|
|
* @return Returns the index into the BTB.
|
|
*/
|
|
inline unsigned getIndex(const Addr &inst_PC);
|
|
|
|
/** Returns the tag bits of a given address.
|
|
* @param inst_PC The branch's address.
|
|
* @return Returns the tag bits.
|
|
*/
|
|
inline Addr getTag(const Addr &inst_PC);
|
|
|
|
/** The actual BTB. */
|
|
std::vector<BTBEntry> btb;
|
|
|
|
/** The number of entries in the BTB. */
|
|
unsigned numEntries;
|
|
|
|
/** The index mask. */
|
|
unsigned idxMask;
|
|
|
|
/** The number of tag bits per entry. */
|
|
unsigned tagBits;
|
|
|
|
/** The tag mask. */
|
|
unsigned tagMask;
|
|
|
|
/** Number of bits to shift PC when calculating index. */
|
|
unsigned instShiftAmt;
|
|
|
|
/** Number of bits to shift PC when calculating tag. */
|
|
unsigned tagShiftAmt;
|
|
};
|
|
|
|
#endif // __CPU_O3_BTB_HH__
|