Nathan Binkert f806a25c9e add support for delaying pio writes until the cache access occurs ... dev/ns_gige.cc: add support for delaying pio writes until the cache access occurs the only write we delay are for CR_TXE and CR_RXE dev/sinic.cc: dev/sinic.hh: the txPioRequest and rxPioRequest things were more or less bogus add support for delaying pio writes until the cache access occurs dev/sinicreg.hh: Add delay_read and delay_write to the register information struct for now, we won't delay any reads, and we'll delay the writes that initiate DMAs python/m5/objects/Ethernet.py: add a parameter to delay pio writes until the timing access actually occurs. --HG-- extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d		2005-11-21 23:43:15 -05:00
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m5	add support for delaying pio writes until the cache access occurs	2005-11-21 23:43:15 -05:00
SConscript	Build options are set via a build_options file in the	2005-08-30 13:18:54 -04:00