753adb38d5
src/arch/mips/SConscript:
"mips import pt.1".
--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
121 lines
3.8 KiB
C++
121 lines
3.8 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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//@TODO: Make sure the naming convention is consistent here.
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////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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def bitfield OPCODE <31:26>;
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def bitfield OPCODE_HI <31:29>;
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def bitfield OPCODE_LO <28:26>;
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def bitfield REGIMM <20:16>;
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def bitfield REGIMM_HI <20:19>;
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def bitfield REGIMM_LO <18:16>;
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def bitfield FUNCTION < 5: 0>;
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def bitfield FUNCTION_HI < 5: 3>;
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def bitfield FUNCTION_LO < 2: 0>;
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def bitfield RS <25:21>;
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def bitfield RS_MSB <25:25>;
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def bitfield RS_HI <25:24>;
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def bitfield RS_LO <23:21>;
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def bitfield RS_SRL <25:22>;
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def bitfield RS_RT <25:16>;
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def bitfield RT <20:16>;
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def bitfield RT_HI <20:19>;
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def bitfield RT_LO <18:16>;
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def bitfield RT_RD <20:11>;
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def bitfield RD <15:11>;
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def bitfield INTIMM <15: 0>;
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def bitfield RS_RT_INTIMM <25: 0>;
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// Floating-point operate format
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def bitfield FMT <25:21>;
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def bitfield FR <25:21>;
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def bitfield FT <20:16>;
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def bitfield FS <15:11>;
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def bitfield FD <10:6>;
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def bitfield ND <17:17>;
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def bitfield TF <16:16>;
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def bitfield MOVCI <16:16>;
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def bitfield MOVCF <16:16>;
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def bitfield SRL <21:21>;
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def bitfield SRLV < 6: 6>;
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def bitfield SA <10: 6>;
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// Floating Point Condition Codes
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def bitfield CC <10:8>;
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def bitfield BRANCH_CC <20:18>;
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// CP0 Register Select
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def bitfield SEL < 2: 0>;
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// INTERRUPTS
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def bitfield SC < 5: 5>;
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// Branch format
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def bitfield OFFSET <15: 0>; // displacement
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// Jmp format
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def bitfield JMPTARG <25: 0>;
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def bitfield HINT <10: 6>;
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def bitfield SYSCALLCODE <25: 6>;
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def bitfield TRAPCODE <15:13>;
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// EXT/INS instructions
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def bitfield MSB <15:11>;
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def bitfield LSB <10: 6>;
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// M5 instructions
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def bitfield M5FUNC <7:0>;
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// DSP instructions
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def bitfield OP <10:6>;
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def bitfield OP_HI <10:9>;
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def bitfield OP_LO <8:6>;
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def bitfield DSPSA <23:21>;
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def bitfield HILOSA <25:20>;
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def bitfield RDDSPMASK <21:16>;
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def bitfield WRDSPMASK <16:11>;
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def bitfield ACSRC <22:21>;
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def bitfield ACDST <12:11>;
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def bitfield BP <12:11>;
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// MT Instructions
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def bitfield POS <10: 6>;
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def bitfield MT_U <5:5>;
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def bitfield MT_H <4:4>;
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