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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
Andreas Hansson 607c277291 stats: Update stats to reflect recent changes to floats 
Mostly just splitting out the floats ops and corresponding
reads/writes.
2016-10-19 06:20:04 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.802883 # Number of seconds simulated
sim_ticks 2802883274000 # Number of ticks simulated
final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1537557 # Simulator instruction rate (inst/s)
host_op_rate 1873488 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29353729253 # Simulator tick rate (ticks/s)
host_mem_usage 598048 # Number of bytes of host memory used
host_seconds 95.49 # Real time elapsed on the host
sim_insts 146815798 # Number of instructions simulated
sim_ops 178892721 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1163300 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 9541412 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 165332 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1112336 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 11983980 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1163300 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 165332 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8870080 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8887644 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 26630 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 149604 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2738 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 17400 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 196397 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 138595 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142986 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 415037 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 3404142 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 58986 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 396854 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4275590 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 415037 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 58986 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3164627 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3170893 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3164627 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 415037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3410394 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 58986 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 396868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7446483 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 7964 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 20338226 # DTB read hits
system.cpu0.dtb.read_misses 6871 # DTB read misses
system.cpu0.dtb.write_hits 16389726 # DTB write hits
system.cpu0.dtb.write_misses 1093 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 20345097 # DTB read accesses
system.cpu0.dtb.write_accesses 16390819 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 36727952 # DTB hits
system.cpu0.dtb.misses 7964 # DTB misses
system.cpu0.dtb.accesses 36735916 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 3358 # Table walker walks requested
system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 97433318 # ITB inst hits
system.cpu0.itb.inst_misses 3358 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 97436676 # ITB inst accesses
system.cpu0.itb.hits 97433318 # DTB hits
system.cpu0.itb.misses 3358 # DTB misses
system.cpu0.itb.accesses 97436676 # DTB accesses
system.cpu0.numPwrStateTransitions 3946 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 5605768522 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed
system.cpu0.committedInsts 95420875 # Number of instructions committed
system.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
system.cpu0.num_func_calls 8000037 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls
system.cpu0.num_int_insts 100755950 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
system.cpu0.num_int_register_reads 182434923 # number of times the integer registers were read
system.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written
system.cpu0.num_mem_refs 37870790 # number of memory refs
system.cpu0.num_load_insts 20595754 # Number of load instructions
system.cpu0.num_store_insts 17275036 # Number of store instructions
system.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles
system.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles
system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles
system.cpu0.Branches 21940702 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction
system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatMisc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::MemRead 20593498 17.62% 85.22% # Class of executed instruction
system.cpu0.op_class::MemWrite 17267541 14.77% 99.99% # Class of executed instruction
system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 116874608 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 693483 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 15689072 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 15689072 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363048 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 363048 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 34796160 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 34796160 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 35142202 # number of overall hits
system.cpu0.dcache.overall_hits::total 35142202 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 295787 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 295787 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18411 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 18411 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 769244 # number of overall misses
system.cpu0.dcache.overall_misses::total 769244 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018504 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048265 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048265 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.021421 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks
system.cpu0.dcache.writebacks::total 693483 # number of writebacks
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 1109362 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits
system.cpu0.icache.overall_hits::total 96325777 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses
system.cpu0.icache.overall_misses::total 1109883 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks
system.cpu0.icache.writebacks::total 1109362 # number of writebacks
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 244755 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15690.306286 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 1516961 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 260398 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.825548 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.001822 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.238695 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065768 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000137 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.957660 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15637 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 527 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 887 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7822 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.954407 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 60864487 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 60864487 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10088 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4467 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 14555 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 510065 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 510065 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 1264919 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 1264919 # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94269 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 94269 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1050188 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1050188 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344415 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 344415 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10088 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4467 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1050188 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 438684 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1503427 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10088 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4467 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1050188 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 438684 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1503427 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 414 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26265 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 26265 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18411 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18411 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175253 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 175253 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59695 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 59695 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135783 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 135783 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 59695 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 311036 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 371145 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 59695 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 311036 # number of overall misses
system.cpu0.l2cache.overall_misses::total 371145 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10362 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4607 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 14969 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510065 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 510065 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264919 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 1264919 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26265 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 26265 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18411 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 18411 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10362 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4607 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 1874572 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10362 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4607 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 1874572 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030389 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.027657 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650236 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650236 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053785 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053785 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282765 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282765 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030389 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053785 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414870 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.197989 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030389 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053785 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414870 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.197989 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.writebacks::writebacks 192868 # number of writebacks
system.cpu0.l2cache.writebacks::total 192868 # number of writebacks
system.cpu0.toL2Bus.snoop_filter.tot_requests 3719490 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859911 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 111560 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109856 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1704 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 510065 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 1292780 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26265 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18411 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44676 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402107 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 5790903 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 530280 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 12377344 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 4224545 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.042934 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.204688 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 4044873 95.75% 95.75% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 177968 4.21% 99.96% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1704 0.04% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 4224545 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 3359 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 12172373 # DTB read hits
system.cpu1.dtb.read_misses 2853 # DTB read misses
system.cpu1.dtb.write_hits 7586083 # DTB write hits
system.cpu1.dtb.write_misses 506 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 12175226 # DTB read accesses
system.cpu1.dtb.write_accesses 7586589 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 19758456 # DTB hits
system.cpu1.dtb.misses 3359 # DTB misses
system.cpu1.dtb.accesses 19761815 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 1734 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 53665127 # ITB inst hits
system.cpu1.itb.inst_misses 1734 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 53666861 # ITB inst accesses
system.cpu1.itb.hits 53665127 # DTB hits
system.cpu1.itb.misses 1734 # DTB misses
system.cpu1.itb.accesses 53666861 # DTB accesses
system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 5605297416 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed
system.cpu1.committedInsts 51394923 # Number of instructions committed
system.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
system.cpu1.num_func_calls 9170267 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls
system.cpu1.num_int_insts 56977163 # number of integer instructions
system.cpu1.num_fp_insts 1792 # number of float instructions
system.cpu1.num_int_register_reads 110657326 # number of times the integer registers were read
system.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written
system.cpu1.num_mem_refs 20023552 # number of memory refs
system.cpu1.num_load_insts 12287954 # Number of load instructions
system.cpu1.num_store_insts 7735598 # Number of store instructions
system.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles
system.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles
system.cpu1.Branches 15216243 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction
system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatMisc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::MemRead 12287438 18.77% 88.18% # Class of executed instruction
system.cpu1.op_class::MemWrite 7734322 11.82% 100.00% # Class of executed instruction
system.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 65451587 # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 191903 # number of replacements
system.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 7396381 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 7396381 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72441 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 72441 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 19253609 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 19253609 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 19303712 # number of overall hits
system.cpu1.dcache.overall_hits::total 19303712 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 92475 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 92475 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22520 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 22520 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 229049 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 229049 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 259766 # number of overall misses
system.cpu1.dcache.overall_misses::total 259766 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237150 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237150 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.013278 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks
system.cpu1.dcache.writebacks::total 191903 # number of writebacks
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 523286 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits
system.cpu1.icache.overall_hits::total 53142419 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses
system.cpu1.icache.overall_misses::total 523798 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 523286 # number of writebacks
system.cpu1.icache.writebacks::total 523286 # number of writebacks
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 45747 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 14812.613567 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 613917 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 60319 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 10.177838 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.372104 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.216207 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.025256 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.903831 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.904090 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1590 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8844 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4115 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 25046952 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 25046952 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3528 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1892 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 120650 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 120650 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 583378 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 583378 # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19790 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 19790 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502408 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 502408 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97451 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 97451 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3528 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1892 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 502408 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 117241 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 625069 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3528 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1892 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 502408 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 117241 # number of overall hits
system.cpu1.l2cache.overall_hits::total 625069 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 299 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 735 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28860 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28860 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22520 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22520 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43825 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 43825 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21390 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 21390 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75158 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 75158 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 299 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 21390 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 118983 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 141108 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 299 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 21390 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 118983 # number of overall misses
system.cpu1.l2cache.overall_misses::total 141108 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3964 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 6155 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120650 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 120650 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 583378 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 583378 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28860 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 28860 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22520 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 22520 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3964 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 766177 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3964 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 766177 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136467 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.119415 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688910 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688910 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040836 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040836 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435423 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435423 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136467 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040836 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503687 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.184172 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136467 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040836 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503687 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.184172 # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.writebacks::writebacks 32289 # number of writebacks
system.cpu1.l2cache.writebacks::total 32289 # number of writebacks
system.cpu1.toL2Bus.snoop_filter.tot_requests 1533143 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773124 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 97275 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90578 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6697 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 120650 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 594539 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28860 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22520 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778567 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2368499 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 295837 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 2333632 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 1767980 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.075142 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.277617 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 1641828 92.86% 92.86% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 119455 6.76% 99.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 6697 0.38% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1767980 # Request fanout histogram
system.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
system.iobus.trans_dist::WriteResp 59419 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36442 # number of replacements
system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses
system.iocache.demand_misses::total 36476 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36476 # number of overall misses
system.iocache.overall_misses::total 36476 # number of overall misses
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 135163 # number of replacements
system.l2c.tags.tagsinuse 65177.726515 # Cycle average of tags in use
system.l2c.tags.total_refs 431584 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 200605 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.151412 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 6643.934415 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032741 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 7087.737158 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 43017.411906 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1645.646531 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 6779.026349 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.101378 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.108150 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.656394 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.025111 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65436 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 15758 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 49214 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.998474 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5327823 # Number of tag accesses
system.l2c.tags.data_accesses 5327823 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 225157 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 225157 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 10195 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 3254 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 13449 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 779 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 1161 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 1940 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 13430 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 3004 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 16434 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 116 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 70 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 42080 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 82797 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 24 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 18817 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 12978 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 156918 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 42080 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 96227 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 24 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 18817 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 15982 # number of demand (read+write) hits
system.l2c.demand_hits::total 173352 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits
system.l2c.overall_hits::cpu0.inst 42080 # number of overall hits
system.l2c.overall_hits::cpu0.data 96227 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 24 # number of overall hits
system.l2c.overall_hits::cpu1.inst 18817 # number of overall hits
system.l2c.overall_hits::cpu1.data 15982 # number of overall hits
system.l2c.overall_hits::total 173352 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 275 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 112 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 387 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 30 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 26 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 56 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 137059 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 15933 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 152992 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 17615 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 12278 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 2573 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 1450 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 33926 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 17615 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 149337 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2573 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 17383 # number of demand (read+write) misses
system.l2c.demand_misses::total 186918 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 17615 # number of overall misses
system.l2c.overall_misses::cpu0.data 149337 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2573 # number of overall misses
system.l2c.overall_misses::cpu1.data 17383 # number of overall misses
system.l2c.overall_misses::total 186918 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 225157 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 225157 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 10470 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3366 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 13836 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 809 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1187 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1996 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 150489 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 18937 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 169426 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 124 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 72 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 59695 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 95075 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 24 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 21390 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 14428 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 190844 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 124 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 59695 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 245564 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 21390 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 33365 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 360270 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 124 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 59695 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 245564 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 21390 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 33365 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 360270 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026266 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.033274 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.027971 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037083 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.021904 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.028056 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.910758 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.841369 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.903002 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.295083 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129140 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.120290 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.100499 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.177768 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.295083 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.608139 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.120290 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.520995 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.518828 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.295083 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.608139 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.120290 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.520995 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.518828 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.writebacks::writebacks 102405 # number of writebacks
system.l2c.writebacks::total 102405 # number of writebacks
system.membus.snoop_filter.tot_requests 459549 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 242014 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 43995 # Transaction distribution
system.membus.trans_dist::ReadResp 78173 # Transaction distribution
system.membus.trans_dist::WriteReq 30844 # Transaction distribution
system.membus.trans_dist::WriteResp 30844 # Transaction distribution
system.membus.trans_dist::WritebackDirty 138595 # Transaction distribution
system.membus.trans_dist::CleanEvict 11037 # Transaction distribution
system.membus.trans_dist::UpgradeReq 47132 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 38991 # Transaction distribution
system.membus.trans_dist::UpgradeResp 461 # Transaction distribution
system.membus.trans_dist::ReadExReq 153373 # Transaction distribution
system.membus.trans_dist::ReadExResp 152974 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 34178 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602273 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 723651 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 833045 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18572232 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18762002 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21094290 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 534369 # Request fanout histogram
system.membus.snoop_fanout::mean 0.010375 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.101327 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 528825 98.96% 98.96% # Request fanout histogram
system.membus.snoop_fanout::1 5544 1.04% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 534369 # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 898844 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 454083 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 154581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 30372 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 29420 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 952 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 337174 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 225157 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 65355 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 40931 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 101494 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 213640 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 213640 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 293175 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1214281 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442535 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1656816 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36095992 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10996714 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 47092706 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 140680 # Total snoops (count)
system.toL2Bus.snoopTraffic 6570496 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 1114107 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.326086 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.470599 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 751764 67.48% 67.48% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 361391 32.44% 99.91% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 952 0.09% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 1114107 # Request fanout histogram
---------- End Simulation Statistics ----------
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