gem5/dev/uart8250.hh
Miguel Serrano 6a8ae7a6a0 ghgfsdf
dev/pciconfigall.cc:
    removed union.
dev/pcidev.cc:
    .
dev/rtcreg.h:
    more macros to avoid magic numbers.
dev/tsunami_io.cc:
    replaced magic numbers, no more advancing RTC as it isn't reaaly necessary.
dev/tsunami_io.hh:
    removed declarations of things that go unused.
dev/uart8250.cc:
    reading the Interrupt ID register should clear TX interrupt flag.
dev/uart8250.hh:
    useful #defines.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
    nothing.
python/m5/objects/Pci.py:
    new PciFake.

--HG--
extra : convert_revision : 88259704f5b215591d1416360180810fcda14d26
2005-07-28 11:47:06 -04:00

95 lines
2.9 KiB
C++

/*
* Copyright (c) 2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file
* Defines a 8250 UART
*/
#ifndef __TSUNAMI_UART_HH__
#define __TSUNAMI_UART_HH__
#include "dev/tsunamireg.h"
#include "base/range.hh"
#include "dev/io_device.hh"
#include "dev/uart.hh"
#define IIR_NOPEND 0x1
#define IIR_RXID 0x4
class SimConsole;
class Platform;
class Uart8250 : public Uart
{
protected:
uint8_t IER, DLAB, LCR, MCR;
class IntrEvent : public Event
{
protected:
Uart8250 *uart;
int intrBit;
public:
IntrEvent(Uart8250 *u, int bit);
virtual void process();
virtual const char *description();
void scheduleIntr();
};
IntrEvent txIntrEvent;
IntrEvent rxIntrEvent;
public:
Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Inform the uart that there is data available.
*/
virtual void dataAvailable();
/**
* Return if we have an interrupt pending
* @return interrupt status
*/
virtual bool intStatus() { return status ? true : false; }
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
#endif // __TSUNAMI_UART_HH__