463aa6d49d
arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
295 lines
9 KiB
C++
295 lines
9 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// Todo: Find all the stuff in ExecContext and ev5 that needs to be
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// specifically designed for this CPU.
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#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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#include "cpu/o3/cpu.hh"
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#include "arch/isa_traits.hh"
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#include "sim/byteswap.hh"
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template <class Impl>
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class AlphaFullCPU : public FullO3CPU<Impl>
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{
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protected:
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typedef AlphaISA::Addr Addr;
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typedef TheISA::IntReg IntReg;
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public:
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typedef typename Impl::Params Params;
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public:
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AlphaFullCPU(Params ¶ms);
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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#endif
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public:
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void regStats();
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#if FULL_SYSTEM
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//Note that the interrupt stuff from the base CPU might be somewhat
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//ISA specific (ie NumInterruptLevels). These functions might not
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//be needed in FullCPU though.
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// void post_interrupt(int int_num, int index);
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// void clear_interrupt(int int_num, int index);
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// void clear_interrupts();
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Fault * translateInstReq(MemReqPtr &req)
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{
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return itb->translate(req);
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}
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Fault * translateDataReadReq(MemReqPtr &req)
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{
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return dtb->translate(req, false);
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}
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Fault * translateDataWriteReq(MemReqPtr &req)
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{
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return dtb->translate(req, true);
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}
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#else
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Fault * dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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Fault * translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault * translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault * translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#endif
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// Later on may want to remove this misc stuff from the regfile and
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// have it handled at this level. Might prove to be an issue when
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// trying to rename source/destination registers...
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uint64_t readUniq()
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{
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return this->regFile.readUniq();
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}
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void setUniq(uint64_t val)
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{
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this->regFile.setUniq(val);
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}
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uint64_t readFpcr()
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{
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return this->regFile.readFpcr();
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}
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void setFpcr(uint64_t val)
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{
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this->regFile.setFpcr(val);
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}
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// Most of the full system code and syscall emulation is not yet
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// implemented. These functions do show what the final interface will
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// look like.
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#if FULL_SYSTEM
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uint64_t *getIpr();
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uint64_t readIpr(int idx, Fault * &fault);
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Fault * setIpr(int idx, uint64_t val);
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int readIntrFlag();
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void setIntrFlag(int val);
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Fault * hwrei();
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bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
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bool inPalMode(uint64_t PC)
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{ return AlphaISA::PcPAL(PC); }
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void trap(Fault * fault);
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bool simPalCheck(int palFunc);
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void processInterrupts();
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#endif
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#if !FULL_SYSTEM
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// Need to change these into regfile calls that directly set a certain
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// register. Actually, these functions should handle most of this
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// functionality by themselves; should look up the rename and then
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// set the register.
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IntReg getSyscallArg(int i)
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{
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return this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
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}
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// used to shift args for indirect syscall
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void setSyscallArg(int i, IntReg val)
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{
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this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
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}
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void setSyscallReturn(int64_t return_value)
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{
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// check for error condition. Alpha syscall convention is to
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// indicate success/failure in reg a3 (r19) and put the
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// return value itself in the standard return value reg (v0).
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const int RegA3 = 19; // only place this is used
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if (return_value >= 0) {
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// no error
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this->xc->regs.intRegFile[RegA3] = 0;
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this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
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} else {
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// got an error, return details
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this->xc->regs.intRegFile[RegA3] = (IntReg) -1;
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this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
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}
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}
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void syscall(short thread_num);
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void squashStages();
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#endif
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void copyToXC();
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void copyFromXC();
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public:
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#if FULL_SYSTEM
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bool palShadowEnabled;
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// Not sure this is used anywhere.
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void intr_post(RegFile *regs, Fault * fault, Addr pc);
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// Actually used within exec files. Implement properly.
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void swapPALShadow(bool use_shadow);
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// Called by CPU constructor. Can implement as I please.
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void initCPU(RegFile *regs);
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// Called by initCPU. Implement as I please.
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void initIPRs(RegFile *regs);
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void halt() { panic("Halt not implemented!\n"); }
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#endif
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template <class T>
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Fault * read(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->flags & LOCKED) {
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MiscRegFile *cregs = &req->xc->regs.miscRegs;
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cregs->lock_addr = req->paddr;
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cregs->lock_flag = true;
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}
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#endif
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Fault * error;
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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template <class T>
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Fault * read(MemReqPtr &req, T &data, int load_idx)
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{
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return this->iew.ldstQueue.read(req, data, load_idx);
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}
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template <class T>
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Fault * write(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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MiscRegFile *cregs;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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cregs = &this->xc->regs.miscRegs;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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req->xc->storeCondFailures = 0;//Needed? [RGD]
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} else {
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req->result = cregs->lock_flag;
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if (!cregs->lock_flag ||
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((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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cregs->lock_flag = false;
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if (((++req->xc->storeCondFailures) % 100000) == 0) {
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std::cerr << "Warning: "
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<< req->xc->storeCondFailures
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<< " consecutive store conditional failures "
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<< "on cpu " << this->cpu_id
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<< std::endl;
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}
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return NoFault;
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}
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else req->xc->storeCondFailures = 0;
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->execContexts.size(); i++){
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cregs = &this->system->execContexts[i]->regs.miscRegs;
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if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
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cregs->lock_flag = false;
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}
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}
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#endif
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return this->mem->write(req, (T)::htog(data));
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}
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template <class T>
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Fault * write(MemReqPtr &req, T &data, int store_idx)
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{
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return this->iew.ldstQueue.write(req, data, store_idx);
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}
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};
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#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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