f721a4d9ad
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class deiffinitions
--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
702 lines
20 KiB
C++
702 lines
20 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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/**
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* Base class for general Alpha memory-format instructions.
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*/
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class Memory : public AlphaStaticInst
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{
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protected:
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/// Memory request flags. See mem_req_base.hh.
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unsigned memAccessFlags;
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/// Pointer to EAComp object.
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const StaticInstPtr eaCompPtr;
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/// Pointer to MemAcc object.
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const StaticInstPtr memAccPtr;
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/// Constructor
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Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr _memAccPtr = nullStaticInstPtr)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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public:
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const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
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const StaticInstPtr &memAccInst() const { return memAccPtr; }
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};
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/**
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* Base class for memory-format instructions using a 32-bit
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* displacement (i.e. most of them).
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*/
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class MemoryDisp32 : public Memory
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{
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protected:
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/// Displacement for EA calculation (signed).
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int32_t disp;
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/// Constructor.
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MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr _memAccPtr = nullStaticInstPtr)
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: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
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disp(MEMDISP)
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{
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}
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};
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/**
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* Base class for a few miscellaneous memory-format insts
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* that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
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* None of these instructions has a destination register either.
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*/
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class MemoryNoDisp : public Memory
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{
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protected:
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/// Constructor
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MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr _memAccPtr = nullStaticInstPtr)
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: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
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flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
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}
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std::string
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MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (r%d)", mnemonic, RB);
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}
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}};
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def format LoadAddress(code) {{
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iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def template LoadStoreDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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protected:
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/**
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* "Fake" effective address computation class for "%(mnemonic)s".
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*/
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class EAComp : public %(base_class)s
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{
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public:
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/// Constructor
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EAComp(MachInst machInst);
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%(BasicExecDeclare)s
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};
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/**
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* "Fake" memory access instruction class for "%(mnemonic)s".
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*/
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class MemAcc : public %(base_class)s
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{
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public:
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/// Constructor
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MemAcc(MachInst machInst);
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%(BasicExecDeclare)s
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};
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public:
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/// Constructor.
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%(class_name)s(MachInst machInst);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template InitiateAccDeclare {{
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Fault * initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template CompleteAccDeclare {{
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Fault * completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template LoadStoreConstructor {{
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/** TODO: change op_class to AddrGenOp or something (requires
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* creating new member of OpClass enum in op_class.hh, updating
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* config files, etc.). */
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inline %(class_name)s::EAComp::EAComp(MachInst machInst)
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: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
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{
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%(ea_constructor)s;
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}
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inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
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: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
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{
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%(memacc_constructor)s;
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}
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inline %(class_name)s::%(class_name)s(MachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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new EAComp(machInst), new MemAcc(machInst))
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{
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%(constructor)s;
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}
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}};
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def template EACompExecute {{
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Fault *
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%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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return fault;
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}
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}};
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def template LoadMemAccExecute {{
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Fault *
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadExecute {{
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Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
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}
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return fault;
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}
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}};
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def template LoadCompleteAcc {{
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Fault * %(class_name)s::completeAcc(uint8_t *data,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_dest_decl)s;
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memcpy(&Mem, data, sizeof(Mem));
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreMemAccExecute {{
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Fault *
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == NoFault) {
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%(code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_dest_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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return fault;
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}
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}};
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def template StoreCompleteAcc {{
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Fault * %(class_name)s::completeAcc(uint8_t *data,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault * fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_dest_decl)s;
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memcpy(&write_result, data, sizeof(write_result));
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MiscMemAccExecute {{
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Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == NoFault) {
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%(code)s;
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}
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return NoFault;
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}
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}};
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def template MiscExecute {{
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Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault * fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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return NoFault;
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}
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}};
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def template MiscInitiateAcc {{
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Fault * %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("Misc instruction does not support split access method!");
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return NoFault;
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}
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}};
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def template MiscCompleteAcc {{
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Fault * %(class_name)s::completeAcc(uint8_t *data,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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panic("Misc instruction does not support split access method!");
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return NoFault;
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}
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}};
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// load instructions use Ra as dest, so check for
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// Ra == 31 to detect nops
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def template LoadNopCheckDecode {{
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{
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AlphaStaticInst *i = new %(class_name)s(machInst);
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if (RA == 31) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
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def template LoadPrefetchCheckDecode {{
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{
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if (RA != 31) {
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return new %(class_name)s(machInst);
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}
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else {
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return new %(class_name)sPrefetch(machInst);
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}
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}
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}};
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let {{
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def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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postacc_code = '', base_class = 'MemoryDisp32',
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decode_template = BasicDecode, exec_template_base = ''):
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# Make sure flags are in lists (convert to lists if not).
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mem_flags = makeList(mem_flags)
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inst_flags = makeList(inst_flags)
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# add hook to get effective addresses into execution trace output.
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ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
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# generate code block objects
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ea_cblk = CodeBlock(ea_code)
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memacc_cblk = CodeBlock(memacc_code)
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postacc_cblk = CodeBlock(postacc_code)
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# Some CPU models execute the memory operation as an atomic unit,
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# while others want to separate them into an effective address
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# computation and a memory access operation. As a result, we need
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# to generate three StaticInst objects. Note that the latter two
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# are nested inside the larger "atomic" one.
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# generate InstObjParams for EAComp object
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ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
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|
|
|
# generate InstObjParams for MemAcc object
|
|
memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
|
|
# in the split execution model, the MemAcc portion is responsible
|
|
# for the post-access code.
|
|
memacc_iop.postacc_code = postacc_cblk.code
|
|
|
|
# generate InstObjParams for InitiateAcc, CompleteAcc object
|
|
# The code used depends on the template being used
|
|
if (exec_template_base == 'Load'):
|
|
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
|
|
completeacc_cblk = CodeBlock(memacc_code + postacc_code)
|
|
elif (exec_template_base == 'Store'):
|
|
initiateacc_cblk = CodeBlock(ea_code + memacc_code)
|
|
completeacc_cblk = CodeBlock(postacc_code)
|
|
else:
|
|
initiateacc_cblk = ''
|
|
completeacc_cblk = ''
|
|
|
|
initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
|
|
inst_flags)
|
|
|
|
completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
|
|
inst_flags)
|
|
|
|
if (exec_template_base == 'Load'):
|
|
initiateacc_iop.ea_code = ea_cblk.code
|
|
initiateacc_iop.memacc_code = memacc_cblk.code
|
|
completeacc_iop.memacc_code = memacc_cblk.code
|
|
completeacc_iop.postacc_code = postacc_cblk.code
|
|
elif (exec_template_base == 'Store'):
|
|
initiateacc_iop.ea_code = ea_cblk.code
|
|
initiateacc_iop.memacc_code = memacc_cblk.code
|
|
completeacc_iop.postacc_code = postacc_cblk.code
|
|
|
|
# generate InstObjParams for unified execution
|
|
cblk = CodeBlock(ea_code + memacc_code + postacc_code)
|
|
iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
|
|
|
|
iop.ea_constructor = ea_cblk.constructor
|
|
iop.ea_code = ea_cblk.code
|
|
iop.memacc_constructor = memacc_cblk.constructor
|
|
iop.memacc_code = memacc_cblk.code
|
|
iop.postacc_code = postacc_cblk.code
|
|
|
|
if mem_flags:
|
|
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
|
|
iop.constructor += s
|
|
memacc_iop.constructor += s
|
|
|
|
# select templates
|
|
memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
|
|
fullExecTemplate = eval(exec_template_base + 'Execute')
|
|
initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
|
|
completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
|
|
|
|
# (header_output, decoder_output, decode_block, exec_output)
|
|
return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
|
|
decode_template.subst(iop),
|
|
EACompExecute.subst(ea_iop)
|
|
+ memAccExecTemplate.subst(memacc_iop)
|
|
+ fullExecTemplate.subst(iop)
|
|
+ initiateAccTemplate.subst(initiateacc_iop)
|
|
+ completeAccTemplate.subst(completeacc_iop))
|
|
}};
|
|
|
|
|
|
def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
|
|
mem_flags = [], inst_flags = []) {{
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
decode_template = LoadNopCheckDecode,
|
|
exec_template_base = 'Load')
|
|
}};
|
|
|
|
|
|
// Note that the flags passed in apply only to the prefetch version
|
|
def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
|
|
mem_flags = [], pf_flags = [], inst_flags = []) {{
|
|
# declare the load instruction object and generate the decode block
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
decode_template = LoadPrefetchCheckDecode,
|
|
exec_template_base = 'Load')
|
|
|
|
# Declare the prefetch instruction object.
|
|
|
|
# Make sure flag args are lists so we can mess with them.
|
|
mem_flags = makeList(mem_flags)
|
|
pf_flags = makeList(pf_flags)
|
|
inst_flags = makeList(inst_flags)
|
|
|
|
pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
|
|
pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
|
|
'IsDataPrefetch', 'MemReadOp']
|
|
|
|
(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
|
|
LoadStoreBase(name, Name + 'Prefetch', ea_code,
|
|
'xc->prefetch(EA, memAccessFlags);',
|
|
pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
|
|
|
|
header_output += pf_header_output
|
|
decoder_output += pf_decoder_output
|
|
exec_output += pf_exec_output
|
|
}};
|
|
|
|
|
|
def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
|
|
mem_flags = [], inst_flags = []) {{
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
exec_template_base = 'Store')
|
|
}};
|
|
|
|
|
|
def format StoreCond(memacc_code, postacc_code,
|
|
ea_code = {{ EA = Rb + disp; }},
|
|
mem_flags = [], inst_flags = []) {{
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
postacc_code, exec_template_base = 'Store')
|
|
}};
|
|
|
|
|
|
// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
|
|
def format MiscPrefetch(ea_code, memacc_code,
|
|
mem_flags = [], inst_flags = []) {{
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
|
|
}};
|
|
|
|
|