Andreas Hansson fccbf8bb45 AddrRange: Simplify AddrRange params Python hierarchy ... This patch simplifies the Range object hierarchy in preparation for an address range class that also allows striping (e.g. selecting a few bits as matching in addition to the range). To extend the AddrRange class to an AddrRegion, the first step is to simplify the hierarchy such that we can make it as lean as possible before adding the new functionality. The only class using Range and MetaRange is AddrRange, and the three classes are now collapsed into one.		2012-09-19 06:15:41 -04:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
Caches.py	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	2011-12-01 00:15:22 -08:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	AddrRange: Simplify AddrRange params Python hierarchy	2012-09-19 06:15:41 -04:00
O3_ARM_v7a.py	prefetcher: Make prefetcher a sim object instead of it being a parameter on cache	2012-02-12 16:07:38 -06:00
Options.py	se.py: support specifying multiple programs via command line	2012-09-09 09:33:45 -05:00
Simulation.py	Standard Switch: Drain the system before switching CPUs	2012-09-12 21:41:37 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00