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gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
Steve Reinhardt 5b08e211ab stats: update for O3 changes 
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
2014-06-22 14:33:09 -07:00

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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
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boot_osflags=a
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init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
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[system.clk_domain]
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voltage_domain=system.voltage_domain
[system.cpu0]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload
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SQEntries=32
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activity=0
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branchPred=system.cpu0.branchPred
cachePorts=200
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clk_domain=system.cpu_clk_domain
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commitToIEWDelay=1
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decodeToRenameDelay=1
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dispatchWidth=8
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dtb=system.cpu0.dtb
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smtCommitPolicy=RoundRobin
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[system.cpu0.dcache.tags]
type=LRU
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[system.cpu0.dtb]
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[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
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system=system
tags=system.cpu0.icache.tags
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mem_side=system.toL2Bus.slave[0]
[system.cpu0.icache.tags]
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[system.cpu0.interrupts]
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[system.cpu0.itb]
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[system.cpu0.tracer]
type=ExeTracer
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[system.cpu0.workload]
type=LiveProcess
cmd=test_atomic 4
cwd=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
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ppid=99
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system=system
uid=100
[system.cpu1]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
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iewToCommitDelay=1
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smtCommitPolicy=RoundRobin
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system=system
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[system.cpu1.branchPred]
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instShiftAmt=2
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predType=tournament
[system.cpu1.dcache]
type=BaseCache
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addr_ranges=0:18446744073709551615
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size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
[system.cpu1.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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size=32768
[system.cpu1.dtb]
type=SparcTLB
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size=64
[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
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[system.cpu1.fuPool.FUList1]
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[system.cpu1.fuPool.FUList2]
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[system.cpu1.fuPool.FUList3]
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opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
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[system.cpu1.fuPool.FUList4]
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[system.cpu1.fuPool.FUList4.opList]
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[system.cpu1.fuPool.FUList5]
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eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu1.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu1.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu1.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu1.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu1.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu1.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu1.fuPool.FUList6.opList
[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu1.fuPool.FUList8.opList
[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu1.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
[system.cpu1.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=32768
[system.cpu1.interrupts]
type=SparcInterrupts
eventq_index=0
[system.cpu1.isa]
type=SparcISA
eventq_index=0
[system.cpu1.itb]
type=SparcTLB
eventq_index=0
size=64
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.cpu2]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu2.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=2
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
eventq_index=0
fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu2.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu2.interrupts
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu2.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu2.dcache.cpu_side
icache_port=system.cpu2.icache.cpu_side
[system.cpu2.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu2.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu2.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
mem_side=system.toL2Bus.slave[5]
[system.cpu2.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=32768
[system.cpu2.dtb]
type=SparcTLB
eventq_index=0
size=64
[system.cpu2.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
eventq_index=0
[system.cpu2.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu2.fuPool.FUList0.opList
[system.cpu2.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu2.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
[system.cpu2.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu2.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu2.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
[system.cpu2.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu2.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu2.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu2.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
[system.cpu2.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu2.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu2.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu2.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu2.fuPool.FUList4.opList
[system.cpu2.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu2.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
[system.cpu2.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu2.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu2.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu2.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu2.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu2.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu2.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu2.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu2.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu2.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu2.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu2.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu2.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu2.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu2.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu2.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu2.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu2.fuPool.FUList6.opList
[system.cpu2.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu2.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
[system.cpu2.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu2.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu2.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu2.fuPool.FUList8.opList
[system.cpu2.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu2.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu2.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.slave[4]
[system.cpu2.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=32768
[system.cpu2.interrupts]
type=SparcInterrupts
eventq_index=0
[system.cpu2.isa]
type=SparcISA
eventq_index=0
[system.cpu2.itb]
type=SparcTLB
eventq_index=0
size=64
[system.cpu2.tracer]
type=ExeTracer
eventq_index=0
[system.cpu3]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu3.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=3
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
eventq_index=0
fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu3.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu3.interrupts
isa=system.cpu3.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu3.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=system.cpu0.workload
dcache_port=system.cpu3.dcache.cpu_side
icache_port=system.cpu3.icache.cpu_side
[system.cpu3.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu3.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu3.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
mem_side=system.toL2Bus.slave[7]
[system.cpu3.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=32768
[system.cpu3.dtb]
type=SparcTLB
eventq_index=0
size=64
[system.cpu3.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
eventq_index=0
[system.cpu3.fuPool.FUList0]
type=FUDesc
children=opList
count=6
eventq_index=0
opList=system.cpu3.fuPool.FUList0.opList
[system.cpu3.fuPool.FUList0.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu3.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
eventq_index=0
opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1
[system.cpu3.fuPool.FUList1.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu3.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu3.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
eventq_index=0
opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2
[system.cpu3.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu3.fuPool.FUList2.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu3.fuPool.FUList2.opList2]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu3.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
eventq_index=0
opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2
[system.cpu3.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu3.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu3.fuPool.FUList3.opList2]
type=OpDesc
eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu3.fuPool.FUList4]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu3.fuPool.FUList4.opList
[system.cpu3.fuPool.FUList4.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu3.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
eventq_index=0
opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
[system.cpu3.fuPool.FUList5.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu3.fuPool.FUList5.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu3.fuPool.FUList5.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu3.fuPool.FUList5.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu3.fuPool.FUList5.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu3.fuPool.FUList5.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu3.fuPool.FUList5.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu3.fuPool.FUList5.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu3.fuPool.FUList5.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu3.fuPool.FUList5.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu3.fuPool.FUList5.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu3.fuPool.FUList5.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu3.fuPool.FUList5.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu3.fuPool.FUList5.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu3.fuPool.FUList5.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu3.fuPool.FUList5.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu3.fuPool.FUList5.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu3.fuPool.FUList5.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu3.fuPool.FUList5.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu3.fuPool.FUList5.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu3.fuPool.FUList6]
type=FUDesc
children=opList
count=0
eventq_index=0
opList=system.cpu3.fuPool.FUList6.opList
[system.cpu3.fuPool.FUList6.opList]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu3.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
eventq_index=0
opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
[system.cpu3.fuPool.FUList7.opList0]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu3.fuPool.FUList7.opList1]
type=OpDesc
eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu3.fuPool.FUList8]
type=FUDesc
children=opList
count=1
eventq_index=0
opList=system.cpu3.fuPool.FUList8.opList
[system.cpu3.fuPool.FUList8.opList]
type=OpDesc
eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu3.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu3.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.slave[6]
[system.cpu3.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=32768
[system.cpu3.interrupts]
type=SparcInterrupts
eventq_index=0
[system.cpu3.isa]
type=SparcISA
eventq_index=0
[system.cpu3.itb]
type=SparcTLB
eventq_index=0
size=64
[system.cpu3.tracer]
type=ExeTracer
eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
eventq_index=0
voltage_domain=system.voltage_domain
[system.l2c]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=4194304
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
[system.physmem]
type=DRAMCtrl
activation_limit=4
addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000
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