405 lines
43 KiB
Text
405 lines
43 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 132 # Number of BTB hits
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global.BPredUnit.BTBLookups 584 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 376 # Number of conditional branches predicted
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global.BPredUnit.lookups 738 # Number of BP lookups
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global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target.
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host_inst_rate 39805 # Simulator instruction rate (inst/s)
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host_mem_usage 153128 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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host_tick_rate 34110715 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2387 # Number of instructions simulated
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sim_seconds 0.000002 # Number of seconds simulated
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sim_ticks 2055000 # Number of ticks simulated
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system.cpu.commit.COM:branches 396 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 3910
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 2950 7544.76%
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1 266 680.31%
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2 336 859.34%
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3 131 335.04%
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4 76 194.37%
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5 65 166.24%
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6 27 69.05%
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7 18 46.04%
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8 41 104.86%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 2576 # Number of instructions committed
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system.cpu.commit.COM:loads 415 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 709 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 2387 # Number of Instructions Simulated
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system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
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system.cpu.cpi 1.723083 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.723083 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 5391.304348 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4669.491525 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 372000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 275500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 5532.142857 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 774500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 401000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 5532.142857 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 4773.809524 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 668 # number of overall hits
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system.cpu.dcache.overall_miss_latency 774500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 140 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 401000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 51.873008 # Cycle average of tags in use
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system.cpu.dcache.total_refs 668 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 771 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode
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system.cpu.fetch.Branches 738 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 654 # Number of cache lines fetched
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system.cpu.fetch.Cycles 1444 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.179431 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.139071 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 4113
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system.cpu.fetch.rateDist.min_value 0
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0 3325 8084.12%
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1 32 77.80%
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2 80 194.51%
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3 50 121.57%
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4 99 240.70%
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5 52 126.43%
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6 39 94.82%
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7 35 85.10%
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8 401 974.96%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 5298.507463 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 4556.451613 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 1065000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 847500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 5298.507463 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency
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system.cpu.icache.demand_hits 453 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 1065000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses
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system.cpu.icache.demand_misses 201 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 847500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 5298.507463 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 4556.451613 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 453 # number of overall hits
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system.cpu.icache.overall_miss_latency 1065000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses
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system.cpu.icache.overall_misses 201 # number of overall misses
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system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 847500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 106.293956 # Cycle average of tags in use
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system.cpu.icache.total_refs 453 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 501 # Number of branches executed
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system.cpu.iew.EXEC:nop 234 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.726477 # Inst execution rate
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system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 333 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 1652 # num instructions consuming a value
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system.cpu.iew.WB:count 2914 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 1321 # num instructions producing a value
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system.cpu.iew.WB:rate 0.708485 # insts written-back per cycle
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system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions
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system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing
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system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
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system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed
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system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed
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system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
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system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly
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system.cpu.ipc 0.580355 # IPC: Instructions Per Cycle
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system.cpu.ipc_total 0.580355 # IPC: Total IPC of All Threads
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system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0.start_dist
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No_OpClass 0 0.00% # Type of FU issued
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IntAlu 2178 70.83% # Type of FU issued
|
|
IntMult 1 0.03% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 561 18.24% # Type of FU issued
|
|
MemWrite 335 10.89% # Type of FU issued
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 2 5.71% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 12 34.29% # attempts to use FU when none available
|
|
MemWrite 21 60.00% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 4113
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 2848 6924.39%
|
|
1 479 1164.60%
|
|
2 276 671.04%
|
|
3 213 517.87%
|
|
4 158 384.15%
|
|
5 86 209.09%
|
|
6 34 82.66%
|
|
7 13 31.61%
|
|
8 6 14.59%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.747629 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4509.259259 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_miss_latency 1217500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_avg_miss_latency 4509.259259 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_latency 1217500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_avg_miss_latency 4509.259259 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_latency 1217500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 270 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 158.313436 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 4113 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 700 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|