74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
616 lines
71 KiB
Text
616 lines
71 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000021 # Number of seconds simulated
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sim_ticks 20764500 # Number of ticks simulated
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final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 44697 # Simulator instruction rate (inst/s)
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host_op_rate 44687 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 174155494 # Simulator tick rate (ticks/s)
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host_mem_usage 232524 # Number of bytes of host memory used
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host_seconds 0.12 # Real time elapsed on the host
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sim_insts 5327 # Number of instructions simulated
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sim_ops 5327 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 423 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 27072 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 27072 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 20696000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 423 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation
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system.physmem.totQLat 3131250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests
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system.physmem.totBusLat 2115000 # Total cycles spent in databus access
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system.physmem.totBankLat 6545000 # Total cycles spent in bank access
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system.physmem.avgQLat 7402.48 # Average queueing delay per request
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system.physmem.avgBankLat 15472.81 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 27875.30 # Average memory access latency
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system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 10.19 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.57 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 358 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 48926.71 # Average gap between requests
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system.membus.throughput 1303763635 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 342 # Transaction distribution
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system.membus.trans_dist::ReadResp 342 # Transaction distribution
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system.membus.trans_dist::ReadExReq 81 # Transaction distribution
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system.membus.trans_dist::ReadExResp 81 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 846 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 27072 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 19.0 # Layer utilization (%)
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system.cpu.branchPred.lookups 1636 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 584 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 41530 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 1472 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3957 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 6246 # Number of cycles cpu stages are processed.
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system.cpu.activity 15.039730 # Percentage of cycles cpu is active
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system.cpu.comLoads 715 # Number of Load instructions committed
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system.cpu.comStores 673 # Number of Store instructions committed
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system.cpu.comBranches 1115 # Number of Branches instructions committed
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system.cpu.comNops 173 # Number of Nop instructions committed
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system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2526 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
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system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 892 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 892 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 366 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70225.409836 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 70225.409836 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 70225.409836 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70225.409836 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 70225.409836 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21114000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 21114000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21114000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 21114000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21114000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 21114000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72556.701031 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72556.701031 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72556.701031 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 72556.701031 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 1313010186 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 852 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 27264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 168.609847 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 141.647687 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 26.962160 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004323 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005146 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20795500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3765500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 24561000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5904000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5904000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 20795500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9669500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 30465000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 20795500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9669500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 30465000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71956.747405 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71047.169811 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71815.789474 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72888.888889 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72888.888889 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72021.276596 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71956.747405 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72160.447761 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72021.276596 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17227750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3116250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20344000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4915500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4915500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17227750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8031750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 25259500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17227750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8031750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 25259500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59611.591696 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58797.169811 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59485.380117 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60685.185185 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.185185 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59611.591696 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59938.432836 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59715.130024 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 84.923213 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 84.923213 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020733 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020733 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 914 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 474 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4316000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4316000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 26761000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 26761000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|