59 lines
5.9 KiB
Text
59 lines
5.9 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.000125 # Number of seconds simulated
|
|
sim_ticks 125334 # Number of ticks simulated
|
|
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000 # Frequency of simulated ticks
|
|
host_inst_rate 24800 # Simulator instruction rate (inst/s)
|
|
host_op_rate 24798 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 534538 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 154892 # Number of bytes of host memory used
|
|
host_seconds 0.23 # Real time elapsed on the host
|
|
sim_insts 5814 # Number of instructions simulated
|
|
sim_ops 5814 # Number of ops (including micro ops) simulated
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1493 # Number of cache demand misses
|
|
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7903 # Number of cache demand accesses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 8 # Number of system calls
|
|
system.cpu.numCycles 125334 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 5814 # Number of instructions committed
|
|
system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
|
|
system.cpu.num_func_calls 194 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 5113 # number of integer instructions
|
|
system.cpu.num_fp_insts 2 # number of float instructions
|
|
system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 2089 # number of memory refs
|
|
system.cpu.num_load_insts 1163 # Number of load instructions
|
|
system.cpu.num_store_insts 926 # Number of store instructions
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 125334 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
---------- End Simulation Statistics ----------
|