984c2a4ff6
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge src/cpu/checker/o3_cpu_builder.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/thread_state.hh: Hand merge. --HG-- rename : cpu/activity.cc => src/cpu/activity.cc rename : cpu/activity.hh => src/cpu/activity.hh rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu_builder.cc => src/cpu/checker/cpu_builder.cc rename : cpu/checker/exec_context.hh => src/cpu/checker/exec_context.hh rename : cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_cpu_builder.cc rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh rename : cpu/o3/dep_graph.hh => src/cpu/o3/dep_graph.hh rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/fu_pool.cc => src/cpu/o3/fu_pool.cc rename : cpu/o3/fu_pool.hh => src/cpu/o3/fu_pool.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq.hh => src/cpu/o3/lsq.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/ozone_impl.hh => src/cpu/ozone/ozone_impl.hh rename : cpu/ozone/simple_impl.hh => src/cpu/ozone/simple_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py extra : convert_revision : b7be30474dd03dd3970e737a9d0489aeb2ead84f
168 lines
5.3 KiB
C++
168 lines
5.3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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// Todo: Create destructor.
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// Have it so that there's a more meaningful name given to the variable
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// that marks the beginning of the FP registers.
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#ifndef __CPU_O3_RENAME_MAP_HH__
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#define __CPU_O3_RENAME_MAP_HH__
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#include <iostream>
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#include <utility>
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#include <vector>
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#include "cpu/o3/free_list.hh"
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//For RegIndex
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#include "arch/isa_traits.hh"
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class SimpleRenameMap
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{
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protected:
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typedef TheISA::RegIndex RegIndex;
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public:
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/**
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* Pair of a logical register and a physical register. Tells the
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* previous mapping of a logical register to a physical register.
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* Used to roll back the rename map to a previous state.
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*/
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typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
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/**
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* Pair of a physical register and a physical register. Used to
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* return the physical register that a logical register has been
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* renamed to, and the previous physical register that the same
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* logical register was previously mapped to.
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*/
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typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
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public:
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/** Default constructor. init() must be called prior to use. */
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SimpleRenameMap() {};
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/** Destructor. */
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~SimpleRenameMap();
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/** Initializes rename map with given parameters. */
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void init(unsigned _numLogicalIntRegs,
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unsigned _numPhysicalIntRegs,
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PhysRegIndex &_int_reg_start,
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unsigned _numLogicalFloatRegs,
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unsigned _numPhysicalFloatRegs,
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PhysRegIndex &_float_reg_start,
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unsigned _numMiscRegs,
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RegIndex _intZeroReg,
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RegIndex _floatZeroReg,
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int id,
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bool bindRegs);
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/** Sets the free list used with this rename map. */
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void setFreeList(SimpleFreeList *fl_ptr);
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//Tell rename map to get a free physical register for a given
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//architected register. Not sure it should have a return value,
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//but perhaps it should have some sort of fault in case there are
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//no free registers.
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RenameInfo rename(RegIndex arch_reg);
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PhysRegIndex lookup(RegIndex phys_reg);
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/**
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* Marks the given register as ready, meaning that its value has been
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* calculated and written to the register file.
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* @param ready_reg The index of the physical register that is now ready.
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*/
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void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg);
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int numFreeEntries();
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private:
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/** Rename Map ID */
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int id;
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/** Number of logical integer registers. */
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int numLogicalIntRegs;
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/** Number of physical integer registers. */
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int numPhysicalIntRegs;
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/** Number of logical floating point registers. */
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int numLogicalFloatRegs;
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/** Number of physical floating point registers. */
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int numPhysicalFloatRegs;
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/** Number of miscellaneous registers. */
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int numMiscRegs;
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/** Number of logical integer + float registers. */
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int numLogicalRegs;
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/** Number of physical integer + float registers. */
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int numPhysicalRegs;
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/** The integer zero register. This implementation assumes it is always
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* zero and never can be anything else.
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*/
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RegIndex intZeroReg;
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/** The floating point zero register. This implementation assumes it is
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* always zero and never can be anything else.
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*/
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RegIndex floatZeroReg;
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class RenameEntry
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{
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public:
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PhysRegIndex physical_reg;
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bool valid;
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RenameEntry()
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: physical_reg(0), valid(false)
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{ }
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};
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private:
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/** Integer rename map. */
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std::vector<RenameEntry> intRenameMap;
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/** Floating point rename map. */
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std::vector<RenameEntry> floatRenameMap;
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private:
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/** Free list interface. */
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SimpleFreeList *freeList;
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};
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#endif //__CPU_O3_RENAME_MAP_HH__
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