gem5/src/arch/sparc/linux
Gabe Black e081615cd9 Now ignore sigaction
src/arch/sparc/isa/operands.isa:
    Added the GSR register as a control register

--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
2006-07-26 03:40:56 -04:00
..
linux.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
linux.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
process.cc Now ignore sigaction 2006-07-26 03:40:56 -04:00
process.hh Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00