gem5/sim/eventq.cc
Steve Reinhardt 25693e9e69 Make include paths explicit and update makefile accordingly.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/fake_syscall.cc:
arch/alpha/faults.cc:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/circlebuf.cc:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/cprintf.cc:
base/cprintf.hh:
base/fast_alloc.cc:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/exec_aout.h:
base/loader/exec_ecoff.h:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/misc.cc:
base/misc.hh:
base/pollevent.cc:
base/pollevent.hh:
base/random.cc:
base/random.hh:
base/range.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/statistics.cc:
base/statistics.hh:
base/str.cc:
base/trace.cc:
base/trace.hh:
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
sim/debug.cc:
sim/eventq.cc:
sim/eventq.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/prog.cc:
sim/prog.hh:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/sim_time.cc:
sim/system.cc:
sim/system.hh:
sim/universe.cc:
test/circletest.cc:
test/cprintftest.cc:
test/initest.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/tap/tap.cc:
    Make include paths explicit.

--HG--
extra : convert_revision : 941cbdc591fd4d3d1d9f095cd58fc23dd2d73840
2003-10-10 11:09:00 -07:00

212 lines
5.3 KiB
C++

/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <iostream>
#include <string>
#include <sstream>
#include <vector>
#include "cpu/full_cpu/smt.hh"
#include "base/misc.hh"
#include "sim/eventq.hh"
#include "base/trace.hh"
#include "sim/universe.hh"
using namespace std;
const string Event::defaultName("event");
//
// Main Event Queue
//
// Events on this queue are processed at the *beginning* of each
// cycle, before the pipeline simulation is performed.
//
EventQueue mainEventQueue("Main Event Queue");
void
EventQueue::insert(Event *event)
{
if (head == NULL || event->when() < head->when() ||
(event->when() == head->when() &&
event->priority() <= head->priority())) {
event->next = head;
head = event;
} else {
Event *prev = head;
Event *curr = head->next;
while (curr) {
if (event->when() <= curr->when() &&
(event->when() < curr->when() ||
event->priority() <= curr->priority()))
break;
prev = curr;
curr = curr->next;
}
event->next = curr;
prev->next = event;
}
}
void
EventQueue::remove(Event *event)
{
if (head == NULL)
return;
if (head == event){
head = event->next;
return;
}
Event *prev = head;
Event *curr = head->next;
while (curr && curr != event) {
prev = curr;
curr = curr->next;
}
if (curr == event)
prev->next = curr->next;
}
void
EventQueue::serviceOne()
{
Event *event = head;
event->clearFlags(Event::Scheduled);
head = event->next;
// handle action
if (!event->squashed())
event->process();
else
event->clearFlags(Event::Squashed);
if (event->getFlags(Event::AutoDelete))
delete event;
}
void
EventQueue::nameChildren()
{
int j = 0;
Event *event = head;
while (event) {
stringstream stream;
ccprintf(stream, "%s.event%d", name(), j++);
event->setName(stream.str());
event = event->next;
}
}
void
EventQueue::serialize()
{
string objects = "";
Event *event = head;
while (event) {
objects += event->name();
objects += " ";
event->serialize();
event = event->next;
}
nameOut("Serialized");
paramOut("objects",objects);
}
void
EventQueue::dump()
{
cprintf("============================================================\n");
cprintf("EventQueue Dump (cycle %d)\n", curTick);
cprintf("------------------------------------------------------------\n");
if (empty())
cprintf("<No Events>\n");
else {
Event *event = head;
while (event) {
event->dump();
event = event->next;
}
}
cprintf("============================================================\n");
}
const char *
Event::description()
{
return "generic";
}
#if TRACING_ON
void
Event::trace(const char *action)
{
// This DPRINTF is unconditional because calls to this function
// are protected by an 'if (DTRACE(Event))' in the inlined Event
// methods.
//
// This is just a default implementation for derived classes where
// it's not worth doing anything special. If you want to put a
// more informative message in the trace, override this method on
// the particular subclass where you have the information that
// needs to be printed.
DPRINTFN("%s event %s @ %d\n", description(), action, when());
}
#endif
void
Event::dump()
{
#if TRACING_ON
cprintf(" Created: %d\n", when_created);
#endif
if (scheduled()) {
#if TRACING_ON
cprintf(" Scheduled at %d\n", when_scheduled);
#endif
cprintf(" Scheduled for %d\n", when());
}
else {
cprintf(" Not Scheduled\n");
}
}