4d44e53736
My change to exec_context.hh probably affected these files to no longer have MemoryController forward declared through a long chain of includes. MemoryController should be forward declared where it is used anyways.
dev/alpha_console.hh:
dev/uart.hh:
dev/uart8250.hh:
Forward declaration of MemoryController.
--HG--
extra : convert_revision : afaac4014e0eb3b6d5d385cd4444b77511e03b51
107 lines
3.3 KiB
C++
107 lines
3.3 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Defines a 8250 UART
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*/
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#ifndef __TSUNAMI_UART_HH__
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#define __TSUNAMI_UART_HH__
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#include "dev/tsunamireg.h"
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#include "base/range.hh"
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#include "dev/io_device.hh"
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#include "dev/uart.hh"
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/* UART8250 Interrupt ID Register
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* bit 0 Interrupt Pending 0 = true, 1 = false
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* bit 2:1 ID of highest priority interrupt
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* bit 7:3 zeroes
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*/
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#define IIR_NOPEND 0x1
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// Interrupt IDs
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#define IIR_MODEM 0x00 /* Modem Status (lowest priority) */
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#define IIR_TXID 0x02 /* Tx Data */
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#define IIR_RXID 0x04 /* Rx Data */
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#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
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class SimConsole;
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class MemoryController;
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class Platform;
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class Uart8250 : public Uart
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{
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protected:
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uint8_t IER, DLAB, LCR, MCR;
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class IntrEvent : public Event
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{
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protected:
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Uart8250 *uart;
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int intrBit;
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public:
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IntrEvent(Uart8250 *u, int bit);
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virtual void process();
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virtual const char *description();
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void scheduleIntr();
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};
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IntrEvent txIntrEvent;
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IntrEvent rxIntrEvent;
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public:
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Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
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Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
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Platform *p);
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virtual Fault read(MemReqPtr &req, uint8_t *data);
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virtual Fault write(MemReqPtr &req, const uint8_t *data);
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/**
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* Inform the uart that there is data available.
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*/
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virtual void dataAvailable();
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/**
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* Return if we have an interrupt pending
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* @return interrupt status
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*/
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virtual bool intStatus() { return status ? true : false; }
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __TSUNAMI_UART_HH__
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