bcc333e920
into zed.eecs.umich.edu:/z/benash/bk/m5
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/rtcreg.h:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/uart8250.cc:
dev/uart8250.hh:
python/m5/objects/Tsunami.py:
Merge code.
--HG--
extra : convert_revision : e97d5dbcc051d2061622201265430d359f995d48
171 lines
5.4 KiB
C
171 lines
5.4 KiB
C
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* List of Tsunami CSRs
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*/
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#ifndef __TSUNAMIREG_H__
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#define __TSUNAMIREG_H__
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#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000)
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// CChip Registers
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#define TSDEV_CC_CSR 0x00
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#define TSDEV_CC_MTR 0x01
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#define TSDEV_CC_MISC 0x02
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#define TSDEV_CC_AAR0 0x04
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#define TSDEV_CC_AAR1 0x05
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#define TSDEV_CC_AAR2 0x06
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#define TSDEV_CC_AAR3 0x07
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#define TSDEV_CC_DIM0 0x08
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#define TSDEV_CC_DIM1 0x09
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#define TSDEV_CC_DIR0 0x0A
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#define TSDEV_CC_DIR1 0x0B
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#define TSDEV_CC_DRIR 0x0C
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#define TSDEV_CC_PRBEN 0x0D
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#define TSDEV_CC_IIC0 0x0E
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#define TSDEV_CC_IIC1 0x0F
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#define TSDEV_CC_MPR0 0x10
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#define TSDEV_CC_MPR1 0x11
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#define TSDEV_CC_MPR2 0x12
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#define TSDEV_CC_MPR3 0x13
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#define TSDEV_CC_DIM2 0x18
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#define TSDEV_CC_DIM3 0x19
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#define TSDEV_CC_DIR2 0x1A
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#define TSDEV_CC_DIR3 0x1B
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#define TSDEV_CC_IIC2 0x1C
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#define TSDEV_CC_IIC3 0x1D
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// BigTsunami Registers
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#define TSDEV_CC_BDIMS 0x1000000
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#define TSDEV_CC_BDIRS 0x2000000
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#define TSDEV_CC_IPIQ 0x20 //0xf01a000800
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#define TSDEV_CC_IPIR 0x21 //0xf01a000840
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#define TSDEV_CC_ITIR 0x22 //0xf01a000880
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// PChip Registers
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#define TSDEV_PC_WSBA0 0x00
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#define TSDEV_PC_WSBA1 0x01
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#define TSDEV_PC_WSBA2 0x02
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#define TSDEV_PC_WSBA3 0x03
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#define TSDEV_PC_WSM0 0x04
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#define TSDEV_PC_WSM1 0x05
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#define TSDEV_PC_WSM2 0x06
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#define TSDEV_PC_WSM3 0x07
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#define TSDEV_PC_TBA0 0x08
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#define TSDEV_PC_TBA1 0x09
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#define TSDEV_PC_TBA2 0x0A
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#define TSDEV_PC_TBA3 0x0B
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#define TSDEV_PC_PCTL 0x0C
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#define TSDEV_PC_PLAT 0x0D
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#define TSDEV_PC_RES 0x0E
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#define TSDEV_PC_PERROR 0x0F
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#define TSDEV_PC_PERRMASK 0x10
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#define TSDEV_PC_PERRSET 0x11
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#define TSDEV_PC_TLBIV 0x12
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#define TSDEV_PC_TLBIA 0x13
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#define TSDEV_PC_PMONCTL 0x14
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#define TSDEV_PC_PMONCNT 0x15
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#define TSDEV_PC_SPST 0x20
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// DChip Registers
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#define TSDEV_DC_DSC 0x20
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#define TSDEV_DC_STR 0x21
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#define TSDEV_DC_DREV 0x22
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#define TSDEV_DC_DSC2 0x23
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// I/O Ports
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#define TSDEV_PIC1_MASK 0x21
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#define TSDEV_PIC2_MASK 0xA1
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#define TSDEV_PIC1_ISR 0x20
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#define TSDEV_PIC2_ISR 0xA0
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#define TSDEV_PIC1_ACK 0x20
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#define TSDEV_PIC2_ACK 0xA0
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#define TSDEV_DMA1_RESET 0x0D
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#define TSDEV_DMA2_RESET 0xDA
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#define TSDEV_DMA1_MODE 0x0B
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#define TSDEV_DMA2_MODE 0xD6
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#define TSDEV_DMA1_MASK 0x0A
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#define TSDEV_DMA2_MASK 0xD4
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#define TSDEV_CTRL_PORTB 0x61
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#define TSDEV_TMR0_DATA 0x40
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#define TSDEV_TMR1_DATA 0x41
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#define TSDEV_TMR2_DATA 0x42
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#define TSDEV_TMR_CTRL 0x43
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#define TSDEV_KBD 0x64
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#define TSDEV_DMA1_CMND 0x08
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#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND
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#define TSDEV_DMA2_CMND 0xD0
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#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND
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#define TSDEV_DMA1_MMASK 0x0F
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#define TSDEV_DMA2_MMASK 0xDE
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/* Added for keyboard accesses */
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#define TSDEV_KBD 0x64
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/* Added for ATA PCI DMA */
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#define ATA_PCI_DMA 0x00
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#define ATA_PCI_DMA2 0x02
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#define ATA_PCI_DMA3 0x16
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#define ATA_PCI_DMA4 0x17
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#define ATA_PCI_DMA5 0x1a
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#define ATA_PCI_DMA6 0x11
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#define ATA_PCI_DMA7 0x14
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#define TSDEV_RTC_ADDR 0x70
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#define TSDEV_RTC_DATA 0x71
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#define PCHIP_PCI0_MEMORY ULL(0x00000000000)
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#define PCHIP_PCI0_IO ULL(0x001FC000000)
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#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)
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#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
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#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
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// UART Defines
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#define UART_IER_RDI 0x01
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#define UART_IER_THRI 0x02
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#define UART_IER_RLSI 0x04
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#define UART_LSR_TEMT 0x40
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#define UART_LSR_THRE 0x20
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#define UART_LSR_DR 0x01
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#define UART_MCR_LOOP 0x10
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// System Control PortB Status Bits
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#define PORTB_SPKR_HIGH 0x20
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#endif // __TSUNAMIREG_H__
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