230 lines
7.4 KiB
C++
230 lines
7.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* PCI Configspace implementation
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include <bitset>
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#include "arch/alpha/ev5.hh"
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#include "base/trace.hh"
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#include "dev/pciconfigall.hh"
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#include "dev/pcidev.hh"
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#include "dev/pcireg.h"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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PciConfigAll::PciConfigAll(const string &name,
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Addr a, MemoryController *mmu,
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HierParams *hier, Bus *pio_bus, Tick pio_latency)
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: PioDevice(name, NULL), addr(a)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (pio_bus) {
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pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
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&PciConfigAll::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * pio_bus->clockRate;
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}
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// Make all the pointers to devices null
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for(int x=0; x < MAX_PCI_DEV; x++)
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for(int y=0; y < MAX_PCI_FUNC; y++)
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devices[x][y] = NULL;
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}
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// If two interrupts share the same line largely bad things will happen.
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// Since we don't track how many times an interrupt was set and correspondingly
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// cleared two devices on the same interrupt line and assert and deassert each
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// others interrupt "line". Interrupts will not work correctly.
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void
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PciConfigAll::startup()
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{
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bitset<256> intLines;
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PciDev *tempDev;
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uint8_t intline;
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for (int x = 0; x < MAX_PCI_DEV; x++) {
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for (int y = 0; y < MAX_PCI_FUNC; y++) {
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if (devices[x][y] != NULL) {
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tempDev = devices[x][y];
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intline = tempDev->interruptLine();
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if (intLines.test(intline))
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warn("Interrupt line %#X is used multiple times"
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"(You probably want to fix this).\n", (uint32_t)intline);
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else
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intLines.set(intline);
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} // devices != NULL
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} // PCI_FUNC
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} // PCI_DEV
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}
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Fault
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PciConfigAll::read(MemReqPtr &req, uint8_t *data)
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{
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n",
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req->vaddr, daddr, req->size);
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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if (devices[device][func] == NULL) {
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switch (req->size) {
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// case sizeof(uint64_t):
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// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
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// return NoFault;
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case sizeof(uint32_t):
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*(uint32_t*)data = 0xFFFFFFFF;
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return NoFault;
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case sizeof(uint16_t):
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*(uint16_t*)data = 0xFFFF;
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return NoFault;
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case sizeof(uint8_t):
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*(uint8_t*)data = 0xFF;
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return NoFault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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} else {
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switch (req->size) {
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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devices[device][func]->readConfig(reg, req->size, data);
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return NoFault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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}
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DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
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daddr, req->size);
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return NoFault;
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}
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Fault
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PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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if (devices[device][func] == NULL)
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panic("Attempting to write to config space on non-existant device\n");
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else if (req->size != sizeof(uint8_t) &&
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req->size != sizeof(uint16_t) &&
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req->size != sizeof(uint32_t))
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panic("invalid access size(?) for PCI configspace!\n");
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DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
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req->vaddr, req->size, *(uint32_t*)data);
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devices[device][func]->writeConfig(reg, req->size, data);
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return NoFault;
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}
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void
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PciConfigAll::serialize(std::ostream &os)
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{
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/*
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* There is no state associated with this object that requires
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* serialization. The only real state are the device pointers
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* which are all setup by the constructor of the PciDev class
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*/
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}
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void
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PciConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
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{
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/*
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* There is no state associated with this object that requires
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* serialization. The only real state are the device pointers
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* which are all setup by the constructor of the PciDev class
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*/
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}
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Tick
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PciConfigAll::cacheAccess(MemReqPtr &req)
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{
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return curTick + pioLatency;
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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SimObjectParam<Bus*> pio_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
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BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask"),
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INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
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CREATE_SIM_OBJECT(PciConfigAll)
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{
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return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
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pio_latency);
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}
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REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
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#endif // DOXYGEN_SHOULD_SKIP_THIS
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