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gem5/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out
Kevin Lim 733a57d45a Update long test refs. 
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini:
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out:
tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out:
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr:
    Update refs.

--HG--
extra : convert_revision : 19483a5a18e76338a3208a58d7460a922377acd3
2007-04-15 22:29:37 -04:00

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[root]
type=Root
dummy=0
[system.physmem]
type=PhysicalMemory
file=
range=[0,134217727]
latency=1
zero=false
[system]
type=System
physmem=system.physmem
mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
clock=1000
width=64
responder_set=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
input=cin
output=cout
env=
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
system=system
uid=100
euid=100
gid=100
egid=100
pid=100
ppid=99
[system.cpu.fuPool.FUList0.opList0]
type=OpDesc
opClass=IntAlu
opLat=1
issueLat=1
[system.cpu.fuPool.FUList0]
type=FUDesc
opList=system.cpu.fuPool.FUList0.opList0
count=6
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
opClass=IntMult
opLat=3
issueLat=1
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
opClass=IntDiv
opLat=20
issueLat=19
[system.cpu.fuPool.FUList1]
type=FUDesc
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
count=2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
opClass=FloatAdd
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
opClass=FloatCmp
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
opClass=FloatCvt
opLat=2
issueLat=1
[system.cpu.fuPool.FUList2]
type=FUDesc
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
count=4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
opClass=FloatMult
opLat=4
issueLat=1
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
opClass=FloatDiv
opLat=12
issueLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
opClass=FloatSqrt
opLat=24
issueLat=24
[system.cpu.fuPool.FUList3]
type=FUDesc
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
count=2
[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
opClass=MemRead
opLat=1
issueLat=1
[system.cpu.fuPool.FUList4]
type=FUDesc
opList=system.cpu.fuPool.FUList4.opList0
count=0
[system.cpu.fuPool.FUList5.opList0]
type=OpDesc
opClass=MemWrite
opLat=1
issueLat=1
[system.cpu.fuPool.FUList5]
type=FUDesc
opList=system.cpu.fuPool.FUList5.opList0
count=0
[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
opClass=MemRead
opLat=1
issueLat=1
[system.cpu.fuPool.FUList6.opList1]
type=OpDesc
opClass=MemWrite
opLat=1
issueLat=1
[system.cpu.fuPool.FUList6]
type=FUDesc
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
count=4
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
opClass=IprAccess
opLat=3
issueLat=3
[system.cpu.fuPool.FUList7]
type=FUDesc
opList=system.cpu.fuPool.FUList7.opList0
count=1
[system.cpu.fuPool]
type=FUPool
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
[system.cpu]
type=DerivO3CPU
clock=1
phase=0
numThreads=1
cpu_id=0
activity=0
workload=system.cpu.workload
checker=null
max_insts_any_thread=0
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
progress_interval=0
cachePorts=200
decodeToFetchDelay=1
renameToFetchDelay=1
iewToFetchDelay=1
commitToFetchDelay=1
fetchWidth=8
renameToDecodeDelay=1
iewToDecodeDelay=1
commitToDecodeDelay=1
fetchToDecodeDelay=1
decodeWidth=8
iewToRenameDelay=1
commitToRenameDelay=1
decodeToRenameDelay=1
renameWidth=8
commitToIEWDelay=1
renameToIEWDelay=2
issueToExecuteDelay=1
dispatchWidth=8
issueWidth=8
wbWidth=8
wbDepth=1
fuPool=system.cpu.fuPool
iewToCommitDelay=1
renameToROBDelay=1
commitWidth=8
squashWidth=8
trapLatency=13
backComSize=5
forwardComSize=5
predType=tournament
localPredictorSize=2048
localCtrBits=2
localHistoryTableSize=2048
localHistoryBits=11
globalPredictorSize=8192
globalCtrBits=2
globalHistoryBits=13
choicePredictorSize=8192
choiceCtrBits=2
BTBEntries=4096
BTBTagSize=16
RASSize=16
LQEntries=32
SQEntries=32
LFSTSize=1024
SSITSize=1024
numPhysIntRegs=256
numPhysFloatRegs=256
numIQEntries=64
numROBEntries=192
smtNumFetchingThreads=1
smtFetchPolicy=SingleThread
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtIQPolicy=Partitioned
smtIQThreshold=100
smtROBPolicy=Partitioned
smtROBThreshold=100
smtCommitPolicy=RoundRobin
instShiftAmt=2
defer_registration=false
function_trace=false
function_trace_start=0
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
latency=1
mshrs=10
tgts_per_mshr=5
write_buffers=8
prioritizeRequests=false
protocol=null
trace_addr=0
hash_delay=1
repl=null
compressed_bus=false
store_compressed=false
adaptive_compression=false
compression_latency=0
block_size=64
max_miss_count=0
addr_range=[0,18446744073709551615]
split=false
split_size=0
lifo=false
two_queue=false
prefetch_miss=false
prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
hit_latency=1
[system.cpu.toL2Bus]
type=Bus
bus_id=0
clock=1000
width=64
responder_set=false
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