Use O3CPU when building instead of AlphaO3CPU. I could use some better python magic in the cpu_models.py file! AUTHORS: add middle initial SConstruct: change from AlphaO3CPU to O3CPU src/cpu/SConscript: edits to build O3CPU instead of AlphaO3CPU src/cpu/cpu_models.py: change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model... Actually, some Python expertise could be used here. The 'env' variable is not passed to this file, so I had to parse through the ARGV to find the ISA... src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use isa_specific.hh src/sim/process.cc: only initi NextNPC if not ALPHA src/cpu/o3/alpha/cpu.cc: alphao3cpu impl src/cpu/o3/alpha/cpu.hh: move AlphaTC to it's own file src/cpu/o3/alpha/cpu_impl.hh: Move AlphaTC to it's own file ... src/cpu/o3/alpha/dyn_inst.cc: src/cpu/o3/alpha/dyn_inst.hh: src/cpu/o3/alpha/dyn_inst_impl.hh: include paths src/cpu/o3/alpha/impl.hh: include paths, set default MaxThreads to 2 instead of 4 src/cpu/o3/alpha/params.hh: set Alpha Specific Params here src/python/m5/objects/O3CPU.py: add O3CPU class src/cpu/o3/SConscript: include isa-specific build files src/cpu/o3/alpha/thread_context.cc: NEW HOME of AlphaTC src/cpu/o3/alpha/thread_context.hh: new home of AlphaTC src/cpu/o3/isa_specific.hh: includes ISA specific files src/cpu/o3/params.hh: base o3 params src/cpu/o3/thread_context.hh: base o3 thread context src/cpu/o3/thread_context_impl.hh: base o3 thead context impl --HG-- rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
173 lines
5 KiB
C++
173 lines
5 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "cpu/o3/alpha/dyn_inst.hh"
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
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InstSeqNum seq_num, O3CPU *cpu)
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: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
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{
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initVars();
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}
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
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: BaseDynInst<Impl>(_staticInst)
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{
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initVars();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::initVars()
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{
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// Make sure to have the renamed register entries set to the same
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// as the normal register entries. It will allow the IQ to work
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// without any modifications.
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for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
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_destRegIdx[i] = this->staticInst->destRegIdx(i);
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}
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for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
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_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
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this->_readySrcRegIdx[i] = 0;
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}
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::execute()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool in_syscall = this->thread->inSyscall;
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this->thread->inSyscall = true;
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this->fault = this->staticInst->execute(this, this->traceData);
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this->thread->inSyscall = in_syscall;
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return this->fault;
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::initiateAcc()
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{
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// @todo: Pretty convoluted way to avoid squashing from happening
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// when using the TC during an instruction's execution
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// (specifically for instructions that have side-effects that use
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// the TC). Fix this.
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bool in_syscall = this->thread->inSyscall;
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this->thread->inSyscall = true;
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this->fault = this->staticInst->initiateAcc(this, this->traceData);
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this->thread->inSyscall = in_syscall;
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return this->fault;
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}
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::completeAcc(Packet *pkt)
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{
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this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
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return this->fault;
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}
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#if FULL_SYSTEM
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template <class Impl>
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Fault
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AlphaDynInst<Impl>::hwrei()
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{
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// Can only do a hwrei when in pal mode.
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if (!this->cpu->inPalMode(this->readPC()))
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return new AlphaISA::UnimplementedOpcodeFault;
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// Set the next PC based on the value of the EXC_ADDR IPR.
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this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
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this->threadNumber));
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// Tell CPU to clear any state it needs to if a hwrei is taken.
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this->cpu->hwrei(this->threadNumber);
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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template <class Impl>
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int
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AlphaDynInst<Impl>::readIntrFlag()
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{
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return this->cpu->readIntrFlag();
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::setIntrFlag(int val)
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{
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this->cpu->setIntrFlag(val);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::inPalMode()
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{
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return this->cpu->inPalMode(this->PC);
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}
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template <class Impl>
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void
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AlphaDynInst<Impl>::trap(Fault fault)
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{
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this->cpu->trap(fault, this->threadNumber);
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}
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template <class Impl>
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bool
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AlphaDynInst<Impl>::simPalCheck(int palFunc)
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{
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return this->cpu->simPalCheck(palFunc, this->threadNumber);
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}
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#else
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template <class Impl>
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void
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AlphaDynInst<Impl>::syscall(int64_t callnum)
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{
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this->cpu->syscall(callnum, this->threadNumber);
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}
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#endif
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