3886c4a8f2
The EIOProcess class was removed recently and it was the only other class which derived from Process. Since every Process invocation is also a LiveProcess invocation, it makes sense to simplify the organization by combining the fields from LiveProcess into Process.
151 lines
5.6 KiB
Python
151 lines
5.6 KiB
Python
# -*- coding: utf-8 -*-
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# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Jason Power
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""" This file creates a single CPU and a two-level cache system.
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This script takes a single parameter which specifies a binary to execute.
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If none is provided it executes 'hello' by default (mostly used for testing)
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See Part 1, Chapter 3: Adding cache to the configuration script in the
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learning_gem5 book for more information about this script.
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This file exports options for the L1 I/D and L2 cache sizes.
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IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
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also needs to be updated. For now, email Jason <power.jg@gmail.com>
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"""
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# import the m5 (gem5) library created when gem5 is built
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import m5
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# import all of the SimObjects
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from m5.objects import *
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# Add the common scripts to our path
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m5.util.addToPath('../../')
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# import the caches which we made
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from caches import *
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# import the SimpleOpts module
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from common import SimpleOpts
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# Set the usage message to display
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SimpleOpts.set_usage("usage: %prog [options] <binary to execute>")
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# Finalize the arguments and grab the opts so we can pass it on to our objects
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(opts, args) = SimpleOpts.parse_args()
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# get ISA for the default binary to run. This is mostly for simple testing
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isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
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# Default to running 'hello', use the compiled ISA to find the binary
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binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
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# Check if there was a binary passed in via the command line and error if
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# there are too many arguments
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if len(args) == 1:
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binary = args[0]
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elif len(args) > 1:
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SimpleOpts.print_help()
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m5.fatal("Expected a binary to execute as positional argument")
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# create the system we are going to simulate
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system = System()
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# Set the clock fequency of the system (and all of its children)
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system.clk_domain = SrcClockDomain()
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system.clk_domain.clock = '1GHz'
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system.clk_domain.voltage_domain = VoltageDomain()
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# Set up the system
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system.mem_mode = 'timing' # Use timing accesses
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system.mem_ranges = [AddrRange('512MB')] # Create an address range
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# Create a simple CPU
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system.cpu = TimingSimpleCPU()
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# Create an L1 instruction and data cache
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system.cpu.icache = L1ICache(opts)
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system.cpu.dcache = L1DCache(opts)
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# Connect the instruction and data caches to the CPU
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system.cpu.icache.connectCPU(system.cpu)
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system.cpu.dcache.connectCPU(system.cpu)
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# Create a memory bus, a coherent crossbar, in this case
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system.l2bus = L2XBar()
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# Hook the CPU ports up to the l2bus
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system.cpu.icache.connectBus(system.l2bus)
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system.cpu.dcache.connectBus(system.l2bus)
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# Create an L2 cache and connect it to the l2bus
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system.l2cache = L2Cache(opts)
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system.l2cache.connectCPUSideBus(system.l2bus)
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# Create a memory bus
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system.membus = SystemXBar()
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# Connect the L2 cache to the membus
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system.l2cache.connectMemSideBus(system.membus)
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# create the interrupt controller for the CPU
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system.cpu.createInterruptController()
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# For x86 only, make sure the interrupts are connected to the memory
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# Note: these are directly connected to the memory bus and are not cached
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if m5.defines.buildEnv['TARGET_ISA'] == "x86":
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system.cpu.interrupts[0].pio = system.membus.master
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system.cpu.interrupts[0].int_master = system.membus.slave
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system.cpu.interrupts[0].int_slave = system.membus.master
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# Connect the system up to the membus
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system.system_port = system.membus.slave
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# Create a DDR3 memory controller
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system.mem_ctrl = DDR3_1600_8x8()
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system.mem_ctrl.range = system.mem_ranges[0]
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system.mem_ctrl.port = system.membus.master
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# Create a process for a simple "Hello World" application
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process = Process()
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# Set the command
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# cmd is a list which begins with the executable (like argv)
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process.cmd = [binary]
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# Set the cpu to use the process as its workload and create thread contexts
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system.cpu.workload = process
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system.cpu.createThreads()
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# set up the root SimObject and start the simulation
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root = Root(full_system = False, system = system)
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# instantiate all of the objects we've created above
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m5.instantiate()
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print "Beginning simulation!"
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exit_event = m5.simulate()
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print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
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