71da1d2157
This patch makes the start and end address private in a move to prevent direct manipulation and matching of ranges based on these fields. This is done so that a transition to ranges with interleaving support is possible. As a result of hiding the start and end, a number of member functions are needed to perform the comparisons and manipulations that previously took place directly on the members. An accessor function is provided for the start address, and a function is added to test if an address is within a range. As a result of the latter the != and == operator is also removed in favour of the member function. A member function that returns a string representation is also created to allow debug printing. In general, this patch does not add any functionality, but it does take us closer to a situation where interleaving (and more cleverness) can be added under the bonnet without exposing it to the user. More on that in a later patch.
374 lines
13 KiB
C++
374 lines
13 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Ali Saidi
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* Andreas Hansson
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* William Wang
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*/
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/**
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* @file
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* Declaration of an abstract bus base class.
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*/
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#ifndef __MEM_BUS_HH__
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#define __MEM_BUS_HH__
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#include <deque>
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#include <set>
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#include "base/addr_range_map.hh"
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#include "base/types.hh"
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#include "mem/mem_object.hh"
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#include "params/BaseBus.hh"
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/**
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* The base bus contains the common elements of the non-coherent and
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* coherent bus. It is an abstract class that does not have any of the
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* functionality relating to the actual reception and transmission of
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* packets, as this is left for the subclasses.
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*
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* The BaseBus is responsible for the basic flow control (busy or
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* not), the administration of retries, and the address decoding.
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*/
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class BaseBus : public MemObject
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{
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protected:
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/**
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* A bus layer is an internal bus structure with its own flow
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* control and arbitration. Hence, a single-layer bus mimics a
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* traditional off-chip tri-state bus (like PCI), where only one
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* set of wires are shared. For on-chip buses, a good starting
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* point is to have three layers, for requests, responses, and
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* snoop responses respectively (snoop requests are instantaneous
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* and do not need any flow control or arbitration). This case is
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* similar to AHB and some OCP configurations.
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*
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* As a further extensions beyond the three-layer bus, a future
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* multi-layer bus has with one layer per connected slave port
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* provides a full or partial crossbar, like AXI, OCP, PCIe etc.
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*
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* The template parameter, PortClass, indicates the destination
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* port type for the bus. The retry list holds either master ports
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* or slave ports, depending on the direction of the layer. Thus,
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* a request layer has a retry list containing slave ports,
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* whereas a response layer holds master ports.
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*/
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template <typename PortClass>
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class Layer : public Drainable
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{
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public:
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/**
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* Create a bus layer and give it a name. The bus layer uses
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* the bus an event manager.
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*
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* @param _bus the bus this layer belongs to
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* @param _name the layer's name
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* @param _clock clock period in ticks
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*/
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Layer(BaseBus& _bus, const std::string& _name, Tick _clock);
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/**
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* Drain according to the normal semantics, so that the bus
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* can tell the layer to drain, and pass an event to signal
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* back when drained.
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*
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* @param de drain event to call once drained
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*
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* @return 1 if busy or waiting to retry, or 0 if idle
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*/
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unsigned int drain(DrainManager *dm);
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/**
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* Get the bus layer's name
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*/
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const std::string name() const { return bus.name() + _name; }
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/**
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* Determine if the bus layer accepts a packet from a specific
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* port. If not, the port in question is also added to the
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* retry list. In either case the state of the layer is updated
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* accordingly.
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*
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* @param port Source port resenting the packet
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*
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* @return True if the bus layer accepts the packet
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*/
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bool tryTiming(PortClass* port);
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/**
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* Deal with a destination port accepting a packet by potentially
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* removing the source port from the retry list (if retrying) and
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* occupying the bus layer accordingly.
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*
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* @param busy_time Time to spend as a result of a successful send
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*/
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void succeededTiming(Tick busy_time);
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/**
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* Deal with a destination port not accepting a packet by
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* potentially adding the source port to the retry list (if
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* not already at the front) and occupying the bus layer
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* accordingly.
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*
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* @param busy_time Time to spend as a result of a failed send
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*/
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void failedTiming(PortClass* port, Tick busy_time);
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/** Occupy the bus layer until until */
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void occupyLayer(Tick until);
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/**
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* Send a retry to the port at the head of the retryList. The
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* caller must ensure that the list is not empty.
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*/
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void retryWaiting();
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/**
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* Handler a retry from a neighbouring module. Eventually this
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* should be all encapsulated in the bus. This wraps
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* retryWaiting by verifying that there are ports waiting
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* before calling retryWaiting.
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*/
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void recvRetry();
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private:
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/** The bus this layer is a part of. */
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BaseBus& bus;
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/** A name for this layer. */
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std::string _name;
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/**
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* We declare an enum to track the state of the bus layer. The
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* starting point is an idle state where the bus layer is
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* waiting for a packet to arrive. Upon arrival, the bus layer
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* transitions to the busy state, where it remains either
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* until the packet transfer is done, or the header time is
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* spent. Once the bus layer leaves the busy state, it can
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* either go back to idle, if no packets have arrived while it
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* was busy, or the bus layer goes on to retry the first port
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* on the retryList. A similar transition takes place from
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* idle to retry if the bus layer receives a retry from one of
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* its connected ports. The retry state lasts until the port
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* in questions calls sendTiming and returns control to the
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* bus layer, or goes to a busy state if the port does not
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* immediately react to the retry by calling sendTiming.
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*/
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enum State { IDLE, BUSY, RETRY };
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/** track the state of the bus layer */
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State state;
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/** the clock speed for the bus layer */
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Tick clock;
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/** manager to signal when drained */
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DrainManager *drainManager;
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/**
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* An array of ports that retry should be called
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* on because the original send failed for whatever reason.
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*/
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std::deque<PortClass*> retryList;
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/**
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* Release the bus layer after being occupied and return to an
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* idle state where we proceed to send a retry to any
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* potential waiting port, or drain if asked to do so.
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*/
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void releaseLayer();
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/** event used to schedule a release of the layer */
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EventWrapper<Layer, &Layer::releaseLayer> releaseEvent;
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};
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/** cycles of overhead per transaction */
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const Cycles headerCycles;
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/** the width of the bus in bytes */
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const uint32_t width;
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typedef AddrRangeMap<PortID>::iterator PortMapIter;
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typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter;
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AddrRangeMap<PortID> portMap;
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AddrRange defaultRange;
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/**
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* Function called by the port when the bus is recieving a range change.
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*
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* @param master_port_id id of the port that received the change
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*/
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void recvRangeChange(PortID master_port_id);
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/** Find which port connected to this bus (if any) should be given a packet
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* with this address.
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* @param addr Address to find port for.
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* @return id of port that the packet should be sent out of.
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*/
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PortID findPort(Addr addr);
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// Cache for the findPort function storing recently used ports from portMap
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struct PortCache {
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bool valid;
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PortID id;
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AddrRange range;
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};
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PortCache portCache[3];
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// Checks the cache and returns the id of the port that has the requested
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// address within its range
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inline PortID checkPortCache(Addr addr) const {
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if (portCache[0].valid && portCache[0].range.contains(addr)) {
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return portCache[0].id;
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}
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if (portCache[1].valid && portCache[1].range.contains(addr)) {
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return portCache[1].id;
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}
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if (portCache[2].valid && portCache[2].range.contains(addr)) {
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return portCache[2].id;
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}
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return InvalidPortID;
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}
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// Clears the earliest entry of the cache and inserts a new port entry
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inline void updatePortCache(short id, const AddrRange& range) {
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portCache[2].valid = portCache[1].valid;
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portCache[2].id = portCache[1].id;
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portCache[2].range = portCache[1].range;
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portCache[1].valid = portCache[0].valid;
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portCache[1].id = portCache[0].id;
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portCache[1].range = portCache[0].range;
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portCache[0].valid = true;
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portCache[0].id = id;
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portCache[0].range = range;
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}
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// Clears the cache. Needs to be called in constructor.
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inline void clearPortCache() {
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portCache[2].valid = false;
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portCache[1].valid = false;
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portCache[0].valid = false;
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}
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/**
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* Return the address ranges the bus is responsible for.
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*
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* @return a list of non-overlapping address ranges
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*/
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AddrRangeList getAddrRanges() const;
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/** Calculate the timing parameters for the packet. Updates the
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* firstWordTime and finishTime fields of the packet object.
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* Returns the tick at which the packet header is completed (which
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* will be all that is sent if the target rejects the packet).
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*/
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Tick calcPacketTiming(PacketPtr pkt);
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/**
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* Ask everyone on the bus what their size is and determine the
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* bus size as either the maximum, or if no device specifies a
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* block size return the default.
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*
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* @return the max of all the sizes or the default if none is set
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*/
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unsigned deviceBlockSize() const;
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/**
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* Remember for each of the master ports of the bus if we got an
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* address range from the connected slave. For convenience, also
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* keep track of if we got ranges from all the slave modules or
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* not.
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*/
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std::vector<bool> gotAddrRanges;
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bool gotAllAddrRanges;
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/** The master and slave ports of the bus */
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std::vector<SlavePort*> slavePorts;
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std::vector<MasterPort*> masterPorts;
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/** Convenience typedefs. */
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typedef std::vector<SlavePort*>::iterator SlavePortIter;
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typedef std::vector<MasterPort*>::iterator MasterPortIter;
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typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter;
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typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter;
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/** Port that handles requests that don't match any of the interfaces.*/
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PortID defaultPortID;
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/** If true, use address range provided by default device. Any
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address not handled by another port and not in default device's
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range will cause a fatal error. If false, just send all
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addresses not handled by another port to default device. */
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const bool useDefaultRange;
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uint32_t blockSize;
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BaseBus(const BaseBusParams *p);
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virtual ~BaseBus();
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public:
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virtual void init();
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/** A function used to return the port associated with this bus object. */
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BaseMasterPort& getMasterPort(const std::string& if_name,
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PortID idx = InvalidPortID);
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BaseSlavePort& getSlavePort(const std::string& if_name,
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PortID idx = InvalidPortID);
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virtual unsigned int drain(DrainManager *dm) = 0;
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};
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#endif //__MEM_BUS_HH__
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