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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
Curtis Dunham c87b717dbd stats: update references
2016-10-13 23:21:40 +01:00

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---------- Begin Simulation Statistics ----------
sim_seconds 51.558698 # Number of seconds simulated
sim_ticks 51558697863000 # Number of ticks simulated
final_tick 51558697863000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167711 # Simulator instruction rate (inst/s)
host_op_rate 197118 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7760882097 # Simulator tick rate (ticks/s)
host_mem_usage 692228 # Number of bytes of host memory used
host_seconds 6643.41 # Real time elapsed on the host
sim_insts 1114173091 # Number of instructions simulated
sim_ops 1309536110 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 691712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 570944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 6573600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 114559048 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 428096 # Number of bytes read from this memory
system.physmem.bytes_read::total 122823400 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6573600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6573600 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 143392768 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 143413348 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 10808 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8921 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 118665 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1789998 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6689 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1935081 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2240512 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2243085 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 13416 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 11074 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 127497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2221915 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8303 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2382205 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 127497 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 127497 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2781156 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2781555 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2781156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 13416 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 11074 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 127497 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2222314 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5163760 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1935081 # Number of read requests accepted
system.physmem.writeReqs 2243085 # Number of write requests accepted
system.physmem.readBursts 1935081 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 2243085 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 123796992 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 48192 # Total number of bytes read from write queue
system.physmem.bytesWritten 143410368 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 122823400 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 143413348 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 753 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2282 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 114857 # Per bank write bursts
system.physmem.perBankRdBursts::1 123887 # Per bank write bursts
system.physmem.perBankRdBursts::2 121380 # Per bank write bursts
system.physmem.perBankRdBursts::3 115864 # Per bank write bursts
system.physmem.perBankRdBursts::4 115150 # Per bank write bursts
system.physmem.perBankRdBursts::5 124779 # Per bank write bursts
system.physmem.perBankRdBursts::6 116343 # Per bank write bursts
system.physmem.perBankRdBursts::7 120532 # Per bank write bursts
system.physmem.perBankRdBursts::8 117169 # Per bank write bursts
system.physmem.perBankRdBursts::9 147715 # Per bank write bursts
system.physmem.perBankRdBursts::10 116324 # Per bank write bursts
system.physmem.perBankRdBursts::11 125031 # Per bank write bursts
system.physmem.perBankRdBursts::12 116553 # Per bank write bursts
system.physmem.perBankRdBursts::13 122187 # Per bank write bursts
system.physmem.perBankRdBursts::14 118707 # Per bank write bursts
system.physmem.perBankRdBursts::15 117850 # Per bank write bursts
system.physmem.perBankWrBursts::0 135590 # Per bank write bursts
system.physmem.perBankWrBursts::1 141676 # Per bank write bursts
system.physmem.perBankWrBursts::2 140587 # Per bank write bursts
system.physmem.perBankWrBursts::3 138605 # Per bank write bursts
system.physmem.perBankWrBursts::4 137623 # Per bank write bursts
system.physmem.perBankWrBursts::5 144276 # Per bank write bursts
system.physmem.perBankWrBursts::6 136529 # Per bank write bursts
system.physmem.perBankWrBursts::7 140386 # Per bank write bursts
system.physmem.perBankWrBursts::8 138327 # Per bank write bursts
system.physmem.perBankWrBursts::9 145050 # Per bank write bursts
system.physmem.perBankWrBursts::10 137213 # Per bank write bursts
system.physmem.perBankWrBursts::11 144076 # Per bank write bursts
system.physmem.perBankWrBursts::12 138694 # Per bank write bursts
system.physmem.perBankWrBursts::13 142077 # Per bank write bursts
system.physmem.perBankWrBursts::14 140963 # Per bank write bursts
system.physmem.perBankWrBursts::15 139115 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 498 # Number of times write queue was full causing retry
system.physmem.totGap 51558696478500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1913796 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 2240512 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1142122 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 697940 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 62817 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 25850 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 642 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 477 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 602 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 504 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1020 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 347 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 302 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 225 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 166 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 107 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 28657 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 36011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 84715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 118224 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 127097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 131612 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 133869 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 139104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 141132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 137785 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 140939 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 143104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 134560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 133279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 134737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 146876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 129080 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 132587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 6051 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 4346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 3556 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 3116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2816 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 2568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 2532 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 2407 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 2309 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 2163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 2226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 2215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1851 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1672 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1609 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1783 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 1764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1548 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 1284 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 1590 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 2274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 1415 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 702 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 1141 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 951139 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 280.933676 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 167.585937 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 307.458614 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 376624 39.60% 39.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 238014 25.02% 64.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 91172 9.59% 74.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 53576 5.63% 79.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 39458 4.15% 83.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 27371 2.88% 86.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 21519 2.26% 89.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 17750 1.87% 90.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 85655 9.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 951139 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 118362 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.342416 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 51.876252 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 118357 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 118362 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 118362 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.931642 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.417353 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 17.979781 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-31 114164 96.45% 96.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-63 1862 1.57% 98.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-95 1234 1.04% 99.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-127 621 0.52% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-159 196 0.17% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-191 102 0.09% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-223 42 0.04% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-255 35 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-287 40 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-319 18 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-351 4 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-383 11 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-415 4 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-479 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-511 7 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-543 6 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-607 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-639 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-767 4 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-895 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1024-1055 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 118362 # Writes before turning the bus around for reads
system.physmem.totQLat 71570448504 # Total ticks spent queuing
system.physmem.totMemAccLat 107839098504 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9671640000 # Total ticks spent in databus transfers
system.physmem.avgQLat 37000.16 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 55750.16 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.69 # Average write queue length when enqueuing
system.physmem.readRowHits 1560611 # Number of row buffer hits during reads
system.physmem.writeRowHits 1663363 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.23 # Row buffer hit rate for writes
system.physmem.avgGap 12340030.64 # Average gap between requests
system.physmem.pageHitRate 77.22 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3363189900 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1787570235 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 6802934880 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 5821719840 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 51899586960.000015 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 51612190140 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 3200334720 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 101759183310 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 76295730720 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 12252381205680 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 12554961718635 # Total energy per rank (pJ)
system.physmem_0.averagePower 243.508122 # Core power per rank (mW)
system.physmem_0.totalIdleTime 51437094541003 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 5396479999 # Time in different power states
system.physmem_0.memoryStateTime::REF 22052840000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 51015251458000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 198686963242 # Time in different power states
system.physmem_0.memoryStateTime::ACT 94153955748 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 223156166011 # Time in different power states
system.physmem_1.actEnergy 3427956840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1822002270 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 7008167040 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 5875188300 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 53218604400.000015 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 52383682290 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 3161186880 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 106497624090 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 77662512480 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 12248740584255 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 12559836053265 # Total energy per rank (pJ)
system.physmem_1.averagePower 243.602662 # Core power per rank (mW)
system.physmem_1.totalIdleTime 51435493097538 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 5216830750 # Time in different power states
system.physmem_1.memoryStateTime::REF 22612324000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 50999709861500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 202245988185 # Time in different power states
system.physmem_1.memoryStateTime::ACT 95365744212 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 233547114353 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu.branchPred.lookups 292003156 # Number of BP lookups
system.cpu.branchPred.condPredicted 199825428 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 13707860 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 209782047 # Number of BTB lookups
system.cpu.branchPred.BTBHits 131422635 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 62.647227 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 37743675 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 403344 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 8164760 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 6089475 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2075285 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 798713 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 1433016 # Table walker walks requested
system.cpu.dtb.walker.walksLong 1433016 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 32195 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277777 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 671696 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 761320 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 2826.976830 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 21785.764506 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535 754204 99.07% 99.07% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071 4652 0.61% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607 981 0.13% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143 445 0.06% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679 347 0.05% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215 34 0.00% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751 244 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 36 0.00% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823 13 0.00% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359 353 0.05% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::655360-720895 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 761320 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 803371 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 26077.733077 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21137.704877 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20668.738137 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-131071 799705 99.54% 99.54% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-262143 2825 0.35% 99.90% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-393215 589 0.07% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-524287 118 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-655359 123 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-786431 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::786432-917503 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::1.17965e+06-1.31072e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 803371 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 1075651264316 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.736998 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.521821 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 1071482592816 99.61% 99.61% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 2636080000 0.25% 99.86% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 763976000 0.07% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 297116500 0.03% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 205516000 0.02% 99.98% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 123566500 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 47691000 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 91565500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 3134000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::18-19 3000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 1075651264316 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 277778 89.61% 89.61% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 32195 10.39% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 309973 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1433016 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1433016 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309973 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309973 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1742989 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 218874380 # DTB read hits
system.cpu.dtb.read_misses 1009020 # DTB read misses
system.cpu.dtb.write_hits 193682033 # DTB write hits
system.cpu.dtb.write_misses 423996 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 89021 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 108 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 17262 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 85593 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 219883400 # DTB read accesses
system.cpu.dtb.write_accesses 194106029 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 412556413 # DTB hits
system.cpu.dtb.misses 1433016 # DTB misses
system.cpu.dtb.accesses 413989429 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 178466 # Table walker walks requested
system.cpu.itb.walker.walksLong 178466 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1508 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 129505 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 20095 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 158371 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1754.443680 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 17709.281636 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-65535 157140 99.22% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-131071 1047 0.66% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-196607 42 0.03% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-327679 14 0.01% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-393215 7 0.00% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::524288-589823 40 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::589824-655359 48 0.03% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 158371 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 151108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29265.005824 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23190.077140 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 30431.733671 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 145001 95.96% 95.96% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 5046 3.34% 99.30% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 391 0.26% 99.56% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 366 0.24% 99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 100 0.07% 99.86% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 51 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 20 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 85 0.06% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::720896-786431 24 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 151108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 912439402568 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.949255 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.219812 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 46367810152 5.08% 5.08% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 866006867916 94.91% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 63907500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 568000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 249000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 912439402568 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 129505 98.85% 98.85% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1508 1.15% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 131013 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178466 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 178466 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 131013 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 131013 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 309479 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 465485773 # ITB inst hits
system.cpu.itb.inst_misses 178466 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 62647 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 443320 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 465664239 # ITB inst accesses
system.cpu.itb.hits 465485773 # DTB hits
system.cpu.itb.misses 178466 # DTB misses
system.cpu.itb.accesses 465664239 # DTB accesses
system.cpu.numPwrStateTransitions 34324 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 17162 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean 2940404395.507225 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 58760863847.973442 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows 7839 45.68% 45.68% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 9288 54.12% 99.80% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988780801904 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total 17162 # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON 1095477627305 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50463220235695 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2190964579 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 794033282 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1302230220 # Number of instructions fetch has processed
system.cpu.fetch.Branches 292003156 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 175255785 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1304336456 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29502488 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 4651258 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 26755 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11711903 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1225327 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 1089 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 465024484 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6899822 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 52313 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 2130737314 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.716190 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.134027 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 1403414987 65.87% 65.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 283475853 13.30% 79.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 89003023 4.18% 83.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 354843451 16.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 2130737314 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.133276 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.594364 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 615599644 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 888388322 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 542818505 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 73189293 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10741550 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 41458105 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 4067803 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1416661162 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 33069720 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 10741550 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 678370602 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 94749069 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 569457122 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 557397759 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 220021212 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1392357267 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 8139910 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 7467928 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 990269 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1135391 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 140197147 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 22858 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1342242693 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2216016664 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1651872272 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1433815 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1263306379 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 78936311 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 44081382 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 39609601 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 160762582 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 223936207 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 198122558 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12861166 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11120462 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1339067750 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 44403277 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1369076757 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4228585 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 73934913 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 42101353 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 368543 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 2130737314 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.642537 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.913709 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 1278640571 60.01% 60.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 452467629 21.24% 81.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 292658965 13.74% 94.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 96618652 4.53% 99.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 10322243 0.48% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 29254 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 2130737314 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 74049078 33.84% 33.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 90108 0.04% 33.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26756 0.01% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 482 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 59033401 26.97% 60.86% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 85651168 39.14% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 55 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 945875031 69.09% 69.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2941932 0.21% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 129428 0.01% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 112221 0.01% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 223931934 16.36% 85.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 196085738 14.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1369076757 # Type of FU issued
system.cpu.iq.rate 0.624874 # Inst issue rate
system.cpu.iq.fu_busy_cnt 218850993 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.159853 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5089559021 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1456673430 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1346855595 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2411384 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 915419 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 886368 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1586411072 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1516623 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5720273 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 17413416 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 22608 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 184689 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 8002869 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 3613750 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 2051788 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 10741550 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 13180703 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 5272349 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1383757283 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 223936207 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 198122558 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 39070088 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 183909 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4898355 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 184689 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4057329 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 6115164 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 10172493 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1355379185 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 218880930 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 12294353 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 286256 # number of nop insts executed
system.cpu.iew.exec_refs 412572980 # number of memory reference insts executed
system.cpu.iew.exec_branches 257403074 # Number of branches executed
system.cpu.iew.exec_stores 193692050 # Number of stores executed
system.cpu.iew.exec_rate 0.618622 # Inst execution rate
system.cpu.iew.wb_sent 1348783541 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1347741963 # cumulative count of insts written-back
system.cpu.iew.wb_producers 576070929 # num instructions producing a value
system.cpu.iew.wb_consumers 948341211 # num instructions consuming a value
system.cpu.iew.wb_rate 0.615136 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.607451 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 63015193 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 44034734 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9698166 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 2116507295 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.618725 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.263721 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 1435626131 67.83% 67.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 397528537 18.78% 86.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 150810671 7.13% 93.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 44606790 2.11% 95.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 36101901 1.71% 97.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 18021060 0.85% 98.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 11293216 0.53% 98.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 5858251 0.28% 99.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 16660738 0.79% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 2116507295 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1114173091 # Number of instructions committed
system.cpu.commit.committedOps 1309536110 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 396642479 # Number of memory references committed
system.cpu.commit.loads 206522790 # Number of loads committed
system.cpu.commit.membars 9192719 # Number of memory barriers committed
system.cpu.commit.branches 249090207 # Number of branches committed
system.cpu.commit.fp_insts 874521 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1196753296 # Number of committed integer instructions.
system.cpu.commit.function_calls 31104441 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 910131481 69.50% 69.50% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2552727 0.19% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 103687 0.01% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 105694 0.01% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 206522790 15.77% 85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 190119689 14.52% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1309536110 # Class of committed instruction
system.cpu.commit.bw_lim_events 16660738 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3462896243 # The number of ROB reads
system.cpu.rob.rob_writes 2759222856 # The number of ROB writes
system.cpu.timesIdled 9103079 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 60227265 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 100926431181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 1114173091 # Number of Instructions Simulated
system.cpu.committedOps 1309536110 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.966449 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.966449 # CPI: Total CPI of All Threads
system.cpu.ipc 0.508531 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.508531 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1609897597 # number of integer regfile reads
system.cpu.int_regfile_writes 948614350 # number of integer regfile writes
system.cpu.fp_regfile_reads 1422281 # number of floating regfile reads
system.cpu.fp_regfile_writes 763660 # number of floating regfile writes
system.cpu.cc_regfile_reads 314738541 # number of cc regfile reads
system.cpu.cc_regfile_writes 315610902 # number of cc regfile writes
system.cpu.misc_regfile_reads 3478507383 # number of misc regfile reads
system.cpu.misc_regfile_writes 44953668 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 13773933 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.982218 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 363424605 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 13774445 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 26.383974 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.982218 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1609792532 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1609792532 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 188105539 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 188105539 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 164299305 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 164299305 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 464298 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 464298 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 335039 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 335039 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4843113 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4843113 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5333928 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5333928 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 352739883 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 352739883 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 353204181 # number of overall hits
system.cpu.dcache.overall_hits::total 353204181 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 12867394 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 12867394 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 18868212 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 18868212 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2064415 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2064415 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1270711 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1270711 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 552556 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 552556 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 33006317 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 33006317 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 35070732 # number of overall misses
system.cpu.dcache.overall_misses::total 35070732 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 226129752000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 226129752000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113756894884 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1113756894884 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30103485720 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 30103485720 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9429427500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 9429427500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 286500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 286500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1369990132604 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1369990132604 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1369990132604 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1369990132604 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 200972933 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 200972933 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 183167517 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 183167517 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2528713 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2528713 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605750 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1605750 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5395669 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5395669 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5333936 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5333936 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 385746200 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 385746200 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 388274913 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 388274913 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064026 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.064026 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103011 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.103011 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816390 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.816390 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791350 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.791350 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102407 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102407 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.085565 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.085565 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.090324 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.090324 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17573.857768 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17573.857768 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59028.216075 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59028.216075 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23690.269243 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23690.269243 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.107428 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.107428 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 35812.500000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 35812.500000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41506.907075 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41506.907075 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39063.630967 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39063.630967 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 29294390 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2113869 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.858186 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 10422476 # number of writebacks
system.cpu.dcache.writebacks::total 10422476 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5755479 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 5755479 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15769683 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 15769683 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6881 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 6881 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 266620 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 266620 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 21532043 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 21532043 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 21532043 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 21532043 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7111915 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7111915 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3098529 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3098529 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2057605 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 2057605 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263830 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1263830 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 285936 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 285936 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 11474274 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 11474274 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 13531879 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 13531879 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 120215948500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 120215948500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164231979720 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 164231979720 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 35080858000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 35080858000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28539216720 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28539216720 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4259524000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4259524000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 278500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 278500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312987144940 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 312987144940 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 348068002940 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 348068002940 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225685500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225685500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225685500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225685500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035387 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035387 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016916 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016916 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813697 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813697 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787065 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787065 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052994 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052994 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029746 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.029746 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034851 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034851 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16903.456875 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16903.456875 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53003.208852 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53003.208852 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17049.364674 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17049.364674 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22581.531314 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22581.531314 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14896.774103 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14896.774103 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 34812.500000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 34812.500000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27277.293966 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27277.293966 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25722.074735 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25722.074735 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184782.307373 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184782.307373 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92376.073893 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92376.073893 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 16962264 # number of replacements
system.cpu.icache.tags.tagsinuse 511.953467 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 447249112 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 16962776 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 26.366505 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 13767456500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.953467 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 481966186 # Number of tag accesses
system.cpu.icache.tags.data_accesses 481966186 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 447249112 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 447249112 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 447249112 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 447249112 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 447249112 # number of overall hits
system.cpu.icache.overall_hits::total 447249112 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 17754074 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17754074 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17754074 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17754074 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17754074 # number of overall misses
system.cpu.icache.overall_misses::total 17754074 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 238230546873 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 238230546873 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 238230546873 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 238230546873 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 238230546873 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 238230546873 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 465003186 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 465003186 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 465003186 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 465003186 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 465003186 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 465003186 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038181 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.038181 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.038181 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.038181 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.038181 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.038181 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13418.359463 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13418.359463 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13418.359463 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13418.359463 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13418.359463 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 22063 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1484 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 14.867251 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 16962264 # number of writebacks
system.cpu.icache.writebacks::total 16962264 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 791074 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 791074 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 791074 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 791074 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 791074 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 791074 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16963000 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 16963000 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 16963000 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 16963000 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 16963000 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 16963000 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 214024505887 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 214024505887 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 214024505887 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 214024505887 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 214024505887 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 214024505887 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036479 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.036479 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036479 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.036479 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12617.137646 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12617.137646 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12617.137646 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12617.137646 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 2409655 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65438.820576 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 59303582 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2471799 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 23.992073 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2677802000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9434.053113 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 385.411867 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 416.493163 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.865899 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 48531.996533 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.143952 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005881 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006355 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101789 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.740539 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61860 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 284 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1041 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5649 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54812 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.943909 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 508249108 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 508249108 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1295823 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 305430 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1601253 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 10422476 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 10422476 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 16959660 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 16959660 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 39331 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 39331 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1728598 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1728598 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16865372 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 16865372 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8990828 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 8990828 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 668361 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 668361 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 1295823 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 305430 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 16865372 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.dtb.walker 1295823 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 305430 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 16865372 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 10719426 # number of overall hits
system.cpu.l2cache.overall_hits::total 29186051 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10808 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8922 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 19730 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4027 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 4027 # number of UpgradeReq misses
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system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1343031 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1343031 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 97409 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 97409 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 448173 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 448173 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 595469 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 595469 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 10808 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 8922 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 97409 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 97409 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1791204 # number of overall misses
system.cpu.l2cache.overall_misses::total 1908343 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1486458000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 980532000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 2466990000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73290500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 73290500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 192000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 192000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140749219500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 140749219500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10783493000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 10783493000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49949086500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49949086500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 569000 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 569000 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1486458000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 980532000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 10783493000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 190698306000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 203948789000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1486458000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 980532000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 10783493000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 190698306000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 203948789000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1306631 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 314352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1620983 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 10422476 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 10422476 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 16959660 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 16959660 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43358 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 43358 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3071629 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3071629 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16962781 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 16962781 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439001 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 9439001 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263830 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1263830 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1306631 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 314352 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 16962781 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 12510630 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 31094394 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1306631 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 314352 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 16962781 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 12510630 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 31094394 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008272 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028382 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.012172 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.092878 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.092878 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437237 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.437237 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005743 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005743 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047481 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047481 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.471162 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.471162 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008272 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028382 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005743 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.143175 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.061373 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008272 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028382 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005743 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.143175 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.061373 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137533.123612 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 109900.470746 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 125037.506336 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18199.776509 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18199.776509 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 48000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 48000 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104799.680350 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104799.680350 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110703.251240 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110703.251240 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111450.458863 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111450.458863 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.955549 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.955549 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 106872.186499 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137533.123612 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 109900.470746 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110703.251240 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106463.756222 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 106872.186499 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 2133882 # number of writebacks
system.cpu.l2cache.writebacks::total 2133882 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10808 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8921 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 19729 # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4027 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4027 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1343031 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1343031 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 97409 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 97409 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 448152 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 448152 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 595469 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 595469 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10808 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8921 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 97409 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1791183 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1908321 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10808 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8921 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 97409 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1791183 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1908321 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 891304000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2269682000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76822000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76822000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 182500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 182500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127318887048 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127318887048 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9809383542 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9809383542 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 45465885070 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 45465885070 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12316948002 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12316948002 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 891304000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9809383542 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172784772118 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 184863837660 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1378378000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 891304000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9809383542 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172784772118 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 184863837660 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804372500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290860000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804372500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290860000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012171 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.092878 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.092878 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437237 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437237 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005743 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.047479 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.047479 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.471162 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.471162 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.061372 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008272 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028379 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005743 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.143173 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061372 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115042.931725 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19076.732059 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19076.732059 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45625 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45625 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94799.663632 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94799.663632 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100703.051484 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100703.051484 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101451.929412 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101451.929412 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20684.448732 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20684.448732 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127533.123612 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 99910.772335 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100703.051484 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96464.053153 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96872.506072 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172277.469429 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.842324 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.675421 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82207.038077 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 62444778 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 31707340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2080 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2080 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 2265526 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 28668320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 12556358 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 16962264 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 3627230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 43361 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 43369 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3071629 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3071629 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 16963000 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1296315 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1263830 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50930633 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41545171 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 782892 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3048631 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 96307327 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171543584 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467959922 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2514816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10453048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 3652471370 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 3035082 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 141349672 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 35524572 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.026277 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.159958 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 34591090 97.37% 97.37% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 933482 2.63% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 35524572 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 59309730487 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 1500879 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 25476019939 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 19475244130 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 468898263 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 1742663628 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230980 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230980 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353764 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334352 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334352 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 41893500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 344000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 25183500 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 36499000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 569168088 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147740000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115471 # number of replacements
system.iocache.tags.tagsinuse 10.450359 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13091904207000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.527977 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.922382 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.220499 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.432649 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039767 # Number of tag accesses
system.iocache.tags.data_accesses 1039767 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8826 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8863 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115490 # number of demand (read+write) misses
system.iocache.demand_misses::total 115530 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115490 # number of overall misses
system.iocache.overall_misses::total 115530 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1926111562 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1931197062 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 13315765026 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13315765026 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 15241876588 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 15247313088 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 15241876588 # number of overall miss cycles
system.iocache.overall_miss_latency::total 15247313088 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8826 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8863 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115490 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115530 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115490 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115530 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 218231.538862 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 217894.286585 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124838.418079 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 124838.418079 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 131977.088964 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 131975.725933 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 131977.088964 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 47583 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3458 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 13.760266 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8826 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8863 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115490 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115530 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115490 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115530 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1484811562 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1488047062 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7975666597 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7975666597 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 9460478159 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9463914659 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 9460478159 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9463914659 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168231.538862 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 167894.286585 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74773.743690 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74773.743690 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 81915.994103 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 81917.377815 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 5147706 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2561464 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 54986 # Transaction distribution
system.membus.trans_dist::ReadResp 629139 # Transaction distribution
system.membus.trans_dist::WriteReq 33703 # Transaction distribution
system.membus.trans_dist::WriteResp 33703 # Transaction distribution
system.membus.trans_dist::WritebackDirty 2240512 # Transaction distribution
system.membus.trans_dist::CleanEvict 283345 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
system.membus.trans_dist::ReadExReq 1342476 # Transaction distribution
system.membus.trans_dist::ReadExResp 1342476 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 574153 # Transaction distribution
system.membus.trans_dist::InvalidateReq 702122 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6871030 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7000692 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237690 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237690 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7238382 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258984332 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 259154386 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7252416 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 266406802 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2841 # Total snoops (count)
system.membus.snoopTraffic 181312 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2712040 # Request fanout histogram
system.membus.snoop_fanout::mean 0.013104 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.113719 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2676502 98.69% 98.69% # Request fanout histogram
system.membus.snoop_fanout::1 35538 1.31% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2712040 # Request fanout histogram
system.membus.reqLayer0.occupancy 104012000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 5608000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 14521699612 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 10216122095 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44869281 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558697863000 # Cumulative time (in ticks) in various power states
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 17162 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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