10c79efe55
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
578 lines
19 KiB
C++
578 lines
19 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Emulation of the Tsunami CChip CSRs
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional/memory_control.hh"
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#include "cpu/intr_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
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MemoryController *mmu, HierParams *hier,
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Bus* pio_bus, Tick pio_latency)
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: PioDevice(name, t), addr(a), tsunami(t)
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{
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mmu->add_child(this, RangeSize(addr, size));
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if (pio_bus) {
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pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
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&TsunamiCChip::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * pio_bus->clockRate;
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}
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drir = 0;
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ipint = 0;
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itint = 0;
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for (int x = 0; x < Tsunami::Max_CPUs; x++)
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{
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dim[x] = 0;
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dir[x] = 0;
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}
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//Put back pointer in tsunami
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tsunami->cchip = this;
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}
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Fault *
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TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
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Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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ExecContext *xc = req->xc;
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switch (req->size) {
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case sizeof(uint64_t):
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if (daddr & TSDEV_CC_BDIMS)
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{
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*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
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return NoFault;
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}
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if (daddr & TSDEV_CC_BDIRS)
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{
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*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
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return NoFault;
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}
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switch(regnum) {
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case TSDEV_CC_CSR:
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*(uint64_t*)data = 0x0;
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return NoFault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR not implemeted\n");
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return NoFault;
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case TSDEV_CC_MISC:
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*(uint64_t*)data = (ipint << 8) & 0xF |
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(itint << 4) & 0xF |
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(xc->cpu_id & 0x3);
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return NoFault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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*(uint64_t*)data = 0;
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return NoFault;
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case TSDEV_CC_DIM0:
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*(uint64_t*)data = dim[0];
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return NoFault;
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case TSDEV_CC_DIM1:
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*(uint64_t*)data = dim[1];
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return NoFault;
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case TSDEV_CC_DIM2:
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*(uint64_t*)data = dim[2];
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return NoFault;
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case TSDEV_CC_DIM3:
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*(uint64_t*)data = dim[3];
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return NoFault;
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case TSDEV_CC_DIR0:
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*(uint64_t*)data = dir[0];
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return NoFault;
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case TSDEV_CC_DIR1:
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*(uint64_t*)data = dir[1];
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return NoFault;
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case TSDEV_CC_DIR2:
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*(uint64_t*)data = dir[2];
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return NoFault;
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case TSDEV_CC_DIR3:
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*(uint64_t*)data = dir[3];
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return NoFault;
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case TSDEV_CC_DRIR:
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*(uint64_t*)data = drir;
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return NoFault;
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN not implemented\n");
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return NoFault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx not implemented\n");
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return NoFault;
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx not implemented\n");
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return NoFault;
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case TSDEV_CC_IPIR:
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*(uint64_t*)data = ipint;
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return NoFault;
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case TSDEV_CC_ITIR:
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*(uint64_t*)data = itint;
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return NoFault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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} // uint64_t
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break;
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case sizeof(uint32_t):
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if (regnum == TSDEV_CC_DRIR) {
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warn("accessing DRIR with 32 bit read, "
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"hopefully your just reading this for timing");
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*(uint32_t*)data = drir;
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} else
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panic("invalid access size(?) for tsunami register!\n");
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return NoFault;
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
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return NoFault;
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}
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Fault *
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TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
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req->vaddr, *(uint64_t*)data, req->size);
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
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Addr regnum = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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bool supportedWrite = false;
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switch (req->size) {
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case sizeof(uint64_t):
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if (daddr & TSDEV_CC_BDIMS)
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{
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int number = (daddr >> 4) & 0x3F;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = *(uint64_t*)data;
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dir[number] = dim[number] & drir;
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for(int x = 0; x < Tsunami::Max_CPUs; x++)
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{
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bitvector = ULL(1) << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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// The bit is now set and it wasn't before (set)
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if((dim[number] & bitvector) && (dir[number] & bitvector))
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{
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in posting dir"
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" interrupt to cpu %d\n", number);
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}
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in clear"
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" dir interrupt to cpu %d\n", number);
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}
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}
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}
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return NoFault;
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}
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switch(regnum) {
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case TSDEV_CC_CSR:
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panic("TSDEV_CC_CSR write\n");
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return NoFault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR write not implemented\n");
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return NoFault;
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case TSDEV_CC_MISC:
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uint64_t ipreq;
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ipreq = (*(uint64_t*)data >> 12) & 0xF;
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//If it is bit 12-15, this is an IPI post
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if (ipreq) {
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reqIPI(ipreq);
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supportedWrite = true;
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}
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//If it is bit 8-11, this is an IPI clear
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uint64_t ipintr;
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ipintr = (*(uint64_t*)data >> 8) & 0xF;
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if (ipintr) {
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clearIPI(ipintr);
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supportedWrite = true;
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}
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//If it is the 4-7th bit, clear the RTC interrupt
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uint64_t itintr;
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itintr = (*(uint64_t*)data >> 4) & 0xF;
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if (itintr) {
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clearITI(itintr);
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supportedWrite = true;
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}
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// ignore NXMs
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if (*(uint64_t*)data & 0x10000000)
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supportedWrite = true;
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if(!supportedWrite)
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panic("TSDEV_CC_MISC write not implemented\n");
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return NoFault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx write not implemeted\n");
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return NoFault;
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case TSDEV_CC_DIM0:
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case TSDEV_CC_DIM1:
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case TSDEV_CC_DIM2:
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case TSDEV_CC_DIM3:
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int number;
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if(regnum == TSDEV_CC_DIM0)
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number = 0;
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else if(regnum == TSDEV_CC_DIM1)
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number = 1;
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else if(regnum == TSDEV_CC_DIM2)
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number = 2;
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else
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number = 3;
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uint64_t bitvector;
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uint64_t olddim;
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uint64_t olddir;
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olddim = dim[number];
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olddir = dir[number];
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dim[number] = *(uint64_t*)data;
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dir[number] = dim[number] & drir;
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for(int x = 0; x < 64; x++)
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{
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bitvector = ULL(1) << x;
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// Figure out which bits have changed
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if ((dim[number] & bitvector) != (olddim & bitvector))
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{
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// The bit is now set and it wasn't before (set)
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if((dim[number] & bitvector) && (dir[number] & bitvector))
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{
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tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
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}
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else if ((olddir & bitvector) &&
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!(dir[number] & bitvector))
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{
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// The bit was set and now its now clear and
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// we were interrupting on that bit before
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tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
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DPRINTF(Tsunami, "dim write resulting in clear"
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" dir interrupt to cpu %d\n",
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x);
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}
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}
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}
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return NoFault;
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case TSDEV_CC_DIR0:
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case TSDEV_CC_DIR1:
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case TSDEV_CC_DIR2:
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case TSDEV_CC_DIR3:
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panic("TSDEV_CC_DIR write not implemented\n");
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case TSDEV_CC_DRIR:
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panic("TSDEV_CC_DRIR write not implemented\n");
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN write not implemented\n");
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
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panic("TSDEV_CC_IICx write not implemented\n");
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case TSDEV_CC_MPR0:
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case TSDEV_CC_MPR1:
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case TSDEV_CC_MPR2:
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case TSDEV_CC_MPR3:
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panic("TSDEV_CC_MPRx write not implemented\n");
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case TSDEV_CC_IPIR:
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clearIPI(*(uint64_t*)data);
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return NoFault;
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case TSDEV_CC_ITIR:
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clearITI(*(uint64_t*)data);
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return NoFault;
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case TSDEV_CC_IPIQ:
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reqIPI(*(uint64_t*)data);
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return NoFault;
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default:
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panic("default in cchip read reached, accessing 0x%x\n");
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}
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return NoFault;
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}
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void
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TsunamiCChip::clearIPI(uint64_t ipintr)
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{
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int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(numcpus <= Tsunami::Max_CPUs);
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if (ipintr) {
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for (int cpunum=0; cpunum < numcpus; cpunum++) {
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// Check each cpu bit
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uint64_t cpumask = ULL(1) << cpunum;
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if (ipintr & cpumask) {
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// Check if there is a pending ipi
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if (ipint & cpumask) {
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ipint &= ~cpumask;
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tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
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DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
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}
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else
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warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
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}
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}
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}
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else
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panic("Big IPI Clear, but not processors indicated\n");
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}
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void
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TsunamiCChip::clearITI(uint64_t itintr)
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{
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int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
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assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (itintr) {
|
|
for (int i=0; i < numcpus; i++) {
|
|
uint64_t cpumask = ULL(1) << i;
|
|
if (itintr & cpumask & itint) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
|
|
itint &= ~cpumask;
|
|
DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big ITI Clear, but not processors indicated\n");
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::reqIPI(uint64_t ipreq)
|
|
{
|
|
int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(numcpus <= Tsunami::Max_CPUs);
|
|
|
|
if (ipreq) {
|
|
for (int cpunum=0; cpunum < numcpus; cpunum++) {
|
|
// Check each cpu bit
|
|
uint64_t cpumask = ULL(1) << cpunum;
|
|
if (ipreq & cpumask) {
|
|
// Check if there is already an ipi (bits 8:11)
|
|
if (!(ipint & cpumask)) {
|
|
ipint |= cpumask;
|
|
tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
|
|
DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
|
|
}
|
|
else
|
|
warn("post IPI for CPU=%d, but IPI already\n", cpunum);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
panic("Big IPI Request, but not processors indicated\n");
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::postRTC()
|
|
{
|
|
int size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
for (int i = 0; i < size; i++) {
|
|
uint64_t cpumask = ULL(1) << i;
|
|
if (!(cpumask & itint)) {
|
|
itint |= cpumask;
|
|
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
|
|
DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::postDRIR(uint32_t interrupt)
|
|
{
|
|
uint64_t bitvector = ULL(1) << interrupt;
|
|
uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
drir |= bitvector;
|
|
|
|
for(int i=0; i < size; i++) {
|
|
dir[i] = dim[i] & drir;
|
|
if (dim[i] & bitvector) {
|
|
tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::clearDRIR(uint32_t interrupt)
|
|
{
|
|
uint64_t bitvector = ULL(1) << interrupt;
|
|
uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
|
|
assert(size <= Tsunami::Max_CPUs);
|
|
|
|
if (drir & bitvector)
|
|
{
|
|
drir &= ~bitvector;
|
|
for(int i=0; i < size; i++) {
|
|
if (dir[i] & bitvector) {
|
|
tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
|
|
DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
|
|
"interrupt %d\n",i, interrupt);
|
|
|
|
}
|
|
dir[i] = dim[i] & drir;
|
|
}
|
|
}
|
|
else
|
|
DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
|
|
}
|
|
|
|
Tick
|
|
TsunamiCChip::cacheAccess(MemReqPtr &req)
|
|
{
|
|
return curTick + pioLatency;
|
|
}
|
|
|
|
|
|
void
|
|
TsunamiCChip::serialize(std::ostream &os)
|
|
{
|
|
SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
SERIALIZE_SCALAR(ipint);
|
|
SERIALIZE_SCALAR(itint);
|
|
SERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
void
|
|
TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
|
|
UNSERIALIZE_SCALAR(ipint);
|
|
UNSERIALIZE_SCALAR(itint);
|
|
UNSERIALIZE_SCALAR(drir);
|
|
}
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
SimObjectParam<Tsunami *> tsunami;
|
|
SimObjectParam<MemoryController *> mmu;
|
|
Param<Addr> addr;
|
|
SimObjectParam<Bus*> pio_bus;
|
|
Param<Tick> pio_latency;
|
|
SimObjectParam<HierParams *> hier;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
INIT_PARAM(tsunami, "Tsunami"),
|
|
INIT_PARAM(mmu, "Memory Controller"),
|
|
INIT_PARAM(addr, "Device Address"),
|
|
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
|
|
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
|
|
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
|
|
|
CREATE_SIM_OBJECT(TsunamiCChip)
|
|
{
|
|
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier,
|
|
pio_bus, pio_latency);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|