b006ad26d4
Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
1600 lines
186 KiB
Text
1600 lines
186 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 47.256536 # Number of seconds simulated
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sim_ticks 47256535705500 # Number of ticks simulated
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final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1118024 # Simulator instruction rate (inst/s)
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host_op_rate 1315296 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 54153885278 # Simulator tick rate (ticks/s)
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host_mem_usage 690972 # Number of bytes of host memory used
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host_seconds 872.63 # Real time elapsed on the host
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sim_insts 975625723 # Number of instructions simulated
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sim_ops 1147772483 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 156864 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 3883124 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 35607176 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 217792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 214080 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 2613000 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 38038064 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 430464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 81291956 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 3883124 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 2613000 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 6496124 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 101151552 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
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system.physmem.bytes_written::total 101172136 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 2451 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 101081 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 556375 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 3403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 3345 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 40935 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 594361 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6726 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1310730 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1580493 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1583067 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 3319 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 82171 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 753487 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 4609 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 4530 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 55294 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 804927 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 9109 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1720227 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 82171 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 55294 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 137465 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2140478 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2140913 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2140478 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 3319 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 82171 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 753922 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 4609 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 4530 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 55294 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 804927 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 9109 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3861140 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.dtb.walker.walks 124170 # Table walker walks requested
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system.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors
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system.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.inst_hits 0 # ITB inst hits
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.read_hits 91996645 # DTB read hits
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system.cpu0.dtb.read_misses 87944 # DTB read misses
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system.cpu0.dtb.write_hits 85085804 # DTB write hits
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system.cpu0.dtb.write_misses 36226 # DTB write misses
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system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.read_accesses 92084589 # DTB read accesses
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system.cpu0.dtb.write_accesses 85122030 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dtb.hits 177082449 # DTB hits
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system.cpu0.dtb.misses 124170 # DTB misses
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system.cpu0.dtb.accesses 177206619 # DTB accesses
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system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.itb.walker.walks 60706 # Table walker walks requested
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system.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors
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system.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
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system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
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system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
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system.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated
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system.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated
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system.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated
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system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst
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system.cpu0.itb.inst_hits 494456191 # ITB inst hits
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system.cpu0.itb.inst_misses 60706 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
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system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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|
system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 494516897 # ITB inst accesses
|
|
system.cpu0.itb.hits 494456191 # DTB hits
|
|
system.cpu0.itb.misses 60706 # DTB misses
|
|
system.cpu0.itb.accesses 494516897 # DTB accesses
|
|
system.cpu0.numCycles 94513084765 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 494222683 # Number of instructions committed
|
|
system.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 28754621 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 532690974 # number of integer instructions
|
|
system.cpu0.num_fp_insts 523276 # number of float instructions
|
|
system.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 177183712 # number of memory refs
|
|
system.cpu0.num_load_insts 92070454 # Number of load instructions
|
|
system.cpu0.num_store_insts 85113258 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles
|
|
system.cpu0.Branches 110567658 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 581576758 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 6248192 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 80310144 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 80310144 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259689 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::total 259689 # number of WriteLineReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039805 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 2039805 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 166131177 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 166131177 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 166345589 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 166345589 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1484857 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1484857 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823193 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::total 823193 # number of WriteLineReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156654 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 156654 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 5600711 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 5600711 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 6375269 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 6375269 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 171731888 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 171731888 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 172720858 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 172720858 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760187 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760187 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071321 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071321 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032613 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.032613 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036911 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.036911 # miss rate for overall accesses
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 6248192 # number of writebacks
|
|
system.cpu0.icache.tags.replacements 5479450 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 489031557 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 5479967 # number of overall misses
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 5479450 # number of writebacks
|
|
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu0.l2cache.tags.replacements 2651590 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16092.484650 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 15457113 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 2667587 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 5.794418 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 15991.608429 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.291374 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.584847 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.976050 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003009 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003148 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.982207 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15920 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1478 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4821 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4797 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4598 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971680 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 394865177 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 394865177 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294372 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156640 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 451012 # number of ReadReq hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4430802 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackDirty_hits::total 4430802 # number of WritebackDirty hits
|
|
system.cpu0.l2cache.WritebackClean_hits::writebacks 7295441 # number of WritebackClean hits
|
|
system.cpu0.l2cache.WritebackClean_hits::total 7295441 # number of WritebackClean hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 774 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::total 774 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 631554 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 631554 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4983798 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadCleanReq_hits::total 4983798 # number of ReadCleanReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2949332 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.ReadSharedReq_hits::total 2949332 # number of ReadSharedReq hits
|
|
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 218231 # number of InvalidateReq hits
|
|
system.cpu0.l2cache.InvalidateReq_hits::total 218231 # number of InvalidateReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 294372 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 156640 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 4983798 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 3580886 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 9015696 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 294372 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 156640 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 4983798 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 3580886 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 9015696 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11531 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8761 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 20292 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140614 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 140614 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156654 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 156654 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 712280 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 712280 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 496169 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadCleanReq_misses::total 496169 # number of ReadCleanReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1236248 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.ReadSharedReq_misses::total 1236248 # number of ReadSharedReq misses
|
|
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 604597 # number of InvalidateReq misses
|
|
system.cpu0.l2cache.InvalidateReq_misses::total 604597 # number of InvalidateReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11531 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8761 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 496169 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 1948528 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 2464989 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11531 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8761 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 496169 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 1948528 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 2464989 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305903 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 471304 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4430802 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackDirty_accesses::total 4430802 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::writebacks 7295441 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.WritebackClean_accesses::total 7295441 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141388 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 141388 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156654 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 156654 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305903 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165401 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 11480685 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305903 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165401 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 11480685 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052968 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.043055 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994526 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994526 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530036 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530036 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090542 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090542 # miss rate for ReadCleanReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295359 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295359 # miss rate for ReadSharedReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734779 # miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734779 # miss rate for InvalidateReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052968 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090542 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352393 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.214707 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037695 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052968 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090542 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352393 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.214707 # miss rate for overall accesses
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.writebacks::writebacks 1558575 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 1558575 # number of writebacks
|
|
system.cpu0.toL2Bus.snoop_filter.tot_requests 24117057 # Total number of requests made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284855 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1785822 # Total number of snoops made to the snoop filter.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785488 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackDirty 4430802 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WritebackClean 7296840 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 141388 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156654 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 298042 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681390 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 37292106 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 6124419 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 30450834 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 0.067260 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.250516 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 28403043 93.28% 93.28% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 2047457 6.72% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 30450834 # Request fanout histogram
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 145097 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 90839106 # DTB read hits
|
|
system.cpu1.dtb.read_misses 112437 # DTB read misses
|
|
system.cpu1.dtb.write_hits 81787747 # DTB write hits
|
|
system.cpu1.dtb.write_misses 32660 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 90951543 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 81820407 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 172626853 # DTB hits
|
|
system.cpu1.dtb.misses 145097 # DTB misses
|
|
system.cpu1.dtb.accesses 172771950 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 61573 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors
|
|
system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 481656543 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 61573 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses
|
|
system.cpu1.itb.hits 481656543 # DTB hits
|
|
system.cpu1.itb.misses 61573 # DTB misses
|
|
system.cpu1.itb.accesses 481718116 # DTB accesses
|
|
system.cpu1.numCycles 94513077683 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 481403040 # Number of instructions committed
|
|
system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 28379648 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 519926686 # number of integer instructions
|
|
system.cpu1.num_fp_insts 376275 # number of float instructions
|
|
system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 172748485 # number of memory refs
|
|
system.cpu1.num_load_insts 90938541 # Number of load instructions
|
|
system.cpu1.num_store_insts 81809944 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles
|
|
system.cpu1.Branches 107246711 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 566836400 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 5963482 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 77626026 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 77626026 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits
|
|
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64910 # number of WriteLineReq hits
|
|
system.cpu1.dcache.WriteLineReq_hits::total 64910 # number of WriteLineReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047982 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 2047982 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 162066607 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 162066607 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 162254892 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 162254892 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 1463877 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 1463877 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses
|
|
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435843 # number of WriteLineReq misses
|
|
system.cpu1.dcache.WriteLineReq_misses::total 435843 # number of WriteLineReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158992 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 158992 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 5269627 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 5269627 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 6059925 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 6059925 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 167336234 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 167336234 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 168314817 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 168314817 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018509 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.018509 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870375 # miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870375 # miss rate for WriteLineReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072041 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072041 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031491 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.031491 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036004 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.036004 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 5963482 # number of writebacks
|
|
system.cpu1.icache.tags.replacements 4804881 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 476906226 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 4805393 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 4804881 # number of writebacks
|
|
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu1.l2cache.tags.replacements 2274505 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 13370.273853 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 14355408 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 2290637 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 6.266994 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 9713557342500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 13266.664229 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 44.449121 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.160502 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.809733 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002713 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003611 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.816057 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5867 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4427 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3923 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 364664430 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 364664430 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349739 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155441 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 505180 # number of ReadReq hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030758 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackDirty_hits::total 4030758 # number of WritebackDirty hits
|
|
system.cpu1.l2cache.WritebackClean_hits::writebacks 6737219 # number of WritebackClean hits
|
|
system.cpu1.l2cache.WritebackClean_hits::total 6737219 # number of WritebackClean hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1036 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::total 1036 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606945 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 606945 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338204 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadCleanReq_hits::total 4338204 # number of ReadCleanReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3075973 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.ReadSharedReq_hits::total 3075973 # number of ReadSharedReq hits
|
|
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 162958 # number of InvalidateReq hits
|
|
system.cpu1.l2cache.InvalidateReq_hits::total 162958 # number of InvalidateReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349739 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155441 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 4338204 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 3682918 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 8526302 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349739 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155441 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 4338204 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 3682918 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 8526302 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12351 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9805 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 22156 # number of ReadReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147585 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 147585 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158992 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 158992 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708546 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 708546 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467189 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadCleanReq_misses::total 467189 # number of ReadCleanReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230120 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.ReadSharedReq_misses::total 1230120 # number of ReadSharedReq misses
|
|
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272650 # number of InvalidateReq misses
|
|
system.cpu1.l2cache.InvalidateReq_misses::total 272650 # number of InvalidateReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12351 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9805 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 467189 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 1938666 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 2428011 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12351 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9805 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 467189 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 1938666 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 2428011 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362090 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165246 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 527336 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030758 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackDirty_accesses::total 4030758 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737219 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.WritebackClean_accesses::total 6737219 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148621 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 148621 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158992 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 158992 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362090 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165246 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 10954313 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362090 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165246 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 10954313 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059336 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.042015 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993029 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993029 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538617 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538617 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097222 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097222 # miss rate for ReadCleanReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285670 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285670 # miss rate for ReadSharedReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625907 # miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625907 # miss rate for InvalidateReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059336 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097222 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344861 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.221649 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034110 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059336 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097222 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344861 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.221649 # miss rate for overall accesses
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.writebacks::writebacks 1199052 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 1199052 # number of writebacks
|
|
system.cpu1.toL2Bus.snoop_filter.tot_requests 22219600 # Total number of requests made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11357015 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1768706 # Total number of snoops made to the snoop filter.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1768522 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030758 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WritebackClean 6737605 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 148621 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158992 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 307613 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18716020 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 34341155 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 5725702 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 28118123 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 0.072932 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.260049 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 26067606 92.71% 92.71% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 2050333 7.29% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 184 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 28118123 # Request fanout histogram
|
|
system.iobus.trans_dist::ReadReq 40311 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40311 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iocache.tags.replacements 115596 # number of replacements
|
|
system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1040892 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1040892 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 115655 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 115615 # number of overall misses
|
|
system.iocache.overall_misses::total 115655 # number of overall misses
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 106694 # number of writebacks
|
|
system.iocache.writebacks::total 106694 # number of writebacks
|
|
system.l2c.tags.replacements 1766126 # number of replacements
|
|
system.l2c.tags.tagsinuse 63106.596515 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 4618110 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 1825499 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 2.529780 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 34858.975183 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.002297 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 102.298868 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 3405.442592 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 8003.318713 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 244.723732 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 389.512702 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 2881.151775 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 13153.170652 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.531906 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001038 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.001561 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.051963 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.122121 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003734 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.005943 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.043963 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.200701 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.962930 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 203 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 59170 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 472 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3156 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 50220 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.003098 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.902863 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 73355182 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 73355182 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 2757627 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 2757627 # number of WritebackDirty hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 19019 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 16164 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 35183 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 2641 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 2463 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 5104 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 198159 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 177179 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 375338 # number of ReadExReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6315 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4649 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.inst 438189 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 723007 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5487 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3779 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.inst 426355 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 685222 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 2293003 # number of ReadSharedReq hits
|
|
system.l2c.InvalidateReq_hits::cpu0.data 118931 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::cpu1.data 103897 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::total 222828 # number of InvalidateReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 6315 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 4649 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 438189 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 921166 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5487 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 3779 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 426355 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 862401 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2668341 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 6315 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 4649 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 438189 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 921166 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5487 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 3779 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 426355 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 862401 # number of overall hits
|
|
system.l2c.overall_hits::total 2668341 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 65379 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 61938 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 127317 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 6666 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 6353 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 13019 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 385718 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 415753 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 801471 # number of ReadExReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2451 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2053 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.inst 57980 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 180523 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3403 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3345 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.inst 40834 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 186956 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 477545 # number of ReadSharedReq misses
|
|
system.l2c.InvalidateReq_misses::cpu0.data 477269 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::cpu1.data 162394 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::total 639663 # number of InvalidateReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 2451 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2053 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 57980 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 566241 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 3403 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 3345 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 40834 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 602709 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 1279016 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 2451 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2053 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 57980 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 566241 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 3403 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 3345 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 40834 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 602709 # number of overall misses
|
|
system.l2c.overall_misses::total 1279016 # number of overall misses
|
|
system.l2c.WritebackDirty_accesses::writebacks 2757627 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 2757627 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 84398 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 78102 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 162500 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 9307 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 8816 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 18123 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 583877 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 592932 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 1176809 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8766 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6702 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.inst 496169 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 903530 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8890 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7124 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.inst 467189 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 872178 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 2770548 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu0.data 596200 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu1.data 266291 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::total 862491 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 8766 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 6702 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 496169 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1487407 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 8890 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 7124 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 467189 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 1465110 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 3947357 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 8766 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 6702 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 496169 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1487407 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 8890 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 7124 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 467189 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 1465110 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 3947357 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.774651 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.793040 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.783489 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.716235 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.720622 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.718369 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.660615 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.701182 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.681054 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.306326 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.116855 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.199797 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.469540 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087404 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.214355 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.172365 # miss rate for ReadSharedReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.800518 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609837 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::total 0.741646 # miss rate for InvalidateReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.306326 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.116855 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.380690 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.469540 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.087404 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.411375 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.324018 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279603 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.306326 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.116855 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.380690 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382790 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.469540 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.087404 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.411375 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.324018 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 1473799 # number of writebacks
|
|
system.l2c.writebacks::total 1473799 # number of writebacks
|
|
system.membus.trans_dist::ReadReq 82185 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 568654 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 38847 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 38847 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 1580493 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 246676 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 346899 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 310542 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 162598 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 787734 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 783864 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 486469 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 741739 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 741739 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6419962 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 6570380 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 6917286 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175247068 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 175458447 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 182857999 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 4621584 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 4621584 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 4621584 # Request fanout histogram
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.snoop_filter.tot_requests 11149977 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 5745476 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1663139 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 131712 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 118684 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 13028 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 3554361 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution
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|
system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 2757627 # Transaction distribution
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|
system.toL2Bus.trans_dist::CleanEvict 2018256 # Transaction distribution
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|
system.toL2Bus.trans_dist::UpgradeReq 359820 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 315646 # Transaction distribution
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|
system.toL2Bus.trans_dist::UpgradeResp 675466 # Transaction distribution
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|
system.toL2Bus.trans_dist::ReadExReq 1363961 # Transaction distribution
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|
system.toL2Bus.trans_dist::ReadExResp 1363961 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 3472174 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 862491 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateResp 862491 # Transaction distribution
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|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9530168 # Packet count per connected master and slave (bytes)
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|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8235967 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 17766135 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255951612 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 230454307 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 486405919 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1999071 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 13268387 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.283691 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.452962 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 9517290 71.73% 71.73% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 3738069 28.17% 99.90% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 13028 0.10% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 13268387 # Request fanout histogram
|
|
|
|
---------- End Simulation Statistics ----------
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