gem5/sim
Kevin Lim 716ceb6c10 Code update for CPU models.
arch/alpha/isa_traits.hh:
    Add in clear functions.
cpu/base.cc:
cpu/base.hh:
    Add in CPU progress event.
cpu/base_dyn_inst.hh:
    Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
    Allow for progress intervals.
cpu/o3/tournament_pred.cc:
    Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Fixes.
cpu/ozone/cpu_builder.cc:
    Allow progress interval.
cpu/ozone/front_end_impl.hh:
    Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
    Remove this.
python/m5/objects/BaseCPU.py:
    Add progress interval.
python/m5/objects/Root.py:
    Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
    Add in stats reset.

--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
2006-08-11 17:42:59 -04:00
..
async.hh Many files: 2005-06-05 05:16:00 -04:00
builder.cc Many files: 2005-06-05 05:16:00 -04:00
builder.hh Many files: 2005-06-05 05:16:00 -04:00
byteswap.hh endian fixes and compiles on mac os x 2006-02-15 01:23:13 -05:00
debug.cc Many files: 2005-06-05 05:16:00 -04:00
debug.hh Many files: 2005-06-05 05:16:00 -04:00
eventq.cc Many files: 2005-06-05 05:16:00 -04:00
eventq.hh Many files: 2005-06-05 05:16:00 -04:00
faults.cc Avoid accessing objects directly within the XC. 2006-03-07 22:23:14 -05:00
faults.hh Some clean up work with faults. 2006-03-07 04:31:38 -05:00
host.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
main.cc Many files: 2005-06-05 05:16:00 -04:00
param.cc fixes for gcc 4.0 2005-09-12 03:01:43 -04:00
param.hh Fixes to build with gcc 4.0. 2005-09-02 21:30:02 -04:00
process.cc Don't access init_regs directly. This does not affect newmem; Steve already changed this in newmem. 2006-03-15 15:38:14 -05:00
process.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pseudo_inst.cc Fix stat typo. 2006-05-25 17:56:01 -04:00
pseudo_inst.hh Add quiesceNs, quiesceTime, quiesceCycles, and m5panic pseudo ops. 2006-02-28 18:41:04 -05:00
root.cc Convert type of max_time and progress_interval parameters 2005-09-01 11:32:58 -04:00
serialize.cc Code update for CPU models. 2006-08-11 17:42:59 -04:00
serialize.hh fix the checkpoint bug 2006-05-12 17:47:23 -04:00
sim_events.cc Move max_time and progress_interval parameters to the Root 2005-06-22 09:59:13 -04:00
sim_events.hh Move max_time and progress_interval parameters to the Root 2005-06-22 09:59:13 -04:00
sim_exit.hh Many files: 2005-06-05 05:16:00 -04:00
sim_object.cc Many files: 2005-06-05 05:16:00 -04:00
sim_object.hh Many files: 2005-06-05 05:16:00 -04:00
startup.cc Many files: 2005-06-05 05:16:00 -04:00
startup.hh Many files: 2005-06-05 05:16:00 -04:00
stat_control.cc Code update for CPU models. 2006-08-11 17:42:59 -04:00
stat_control.hh Many files: 2005-06-05 05:16:00 -04:00
stats.hh Many files: 2005-06-05 05:16:00 -04:00
syscall_emul.cc fix merging issues 2006-03-09 16:17:10 -05:00
syscall_emul.hh Merge zizzer:/bk/multiarch 2006-03-09 15:56:42 -05:00
system.cc Merge zizzer:/bk/m5 2006-03-03 14:25:26 -05:00
system.hh First cut at moving alpha specefic stuff out of /sim/system* into 2006-03-03 14:24:15 -05:00
vptr.hh Changed targetarch to just arch. 2006-02-27 05:35:43 -05:00