716ceb6c10
arch/alpha/isa_traits.hh:
Add in clear functions.
cpu/base.cc:
cpu/base.hh:
Add in CPU progress event.
cpu/base_dyn_inst.hh:
Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
Allow for progress intervals.
cpu/o3/tournament_pred.cc:
Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Fixes.
cpu/ozone/cpu_builder.cc:
Allow progress interval.
cpu/ozone/front_end_impl.hh:
Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
Remove this.
python/m5/objects/BaseCPU.py:
Add progress interval.
python/m5/objects/Root.py:
Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
Add in stats reset.
--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
163 lines
5.6 KiB
C++
163 lines
5.6 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "cpu/checker/cpu.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/o3/alpha_dyn_inst.hh"
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#include "cpu/o3/alpha_impl.hh"
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#include "mem/base_mem.hh"
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#include "sim/builder.hh"
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#include "sim/process.hh"
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#include "sim/sim_object.hh"
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/**
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* Specific non-templated derived class used for SimObject configuration.
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*/
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class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
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{
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public:
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O3Checker(Params *p)
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: Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
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{ }
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};
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////////////////////////////////////////////////////////////////////////
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//
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// CheckerCPU Simulation Object
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//
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
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Param<Counter> max_insts_any_thread;
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Param<Counter> max_insts_all_threads;
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Param<Counter> max_loads_any_thread;
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Param<Counter> max_loads_all_threads;
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Param<Tick> progress_interval;
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#if FULL_SYSTEM
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SimObjectParam<AlphaITB *> itb;
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SimObjectParam<AlphaDTB *> dtb;
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SimObjectParam<FunctionalMemory *> mem;
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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Param<Tick> profile;
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#else
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SimObjectParam<Process *> workload;
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#endif // FULL_SYSTEM
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Param<int> clock;
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SimObjectParam<BaseMem *> icache;
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SimObjectParam<BaseMem *> dcache;
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Param<bool> defer_registration;
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Param<bool> exitOnError;
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Param<bool> updateOnError;
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Param<bool> function_trace;
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Param<Tick> function_trace_start;
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END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
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BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
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INIT_PARAM(max_insts_any_thread,
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"terminate when any thread reaches this inst count"),
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INIT_PARAM(max_insts_all_threads,
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"terminate when all threads have reached this inst count"),
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INIT_PARAM(max_loads_any_thread,
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"terminate when any thread reaches this load count"),
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INIT_PARAM(max_loads_all_threads,
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"terminate when all threads have reached this load count"),
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INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
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#if FULL_SYSTEM
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INIT_PARAM(itb, "Instruction TLB"),
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INIT_PARAM(dtb, "Data TLB"),
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INIT_PARAM(mem, "memory"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu_id, "processor ID"),
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INIT_PARAM(profile, ""),
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#else
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INIT_PARAM(workload, "processes to run"),
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#endif // FULL_SYSTEM
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INIT_PARAM(clock, "clock speed"),
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INIT_PARAM(icache, "L1 instruction cache object"),
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INIT_PARAM(dcache, "L1 data cache object"),
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INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
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INIT_PARAM(exitOnError, "exit on error"),
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INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
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INIT_PARAM(function_trace, "Enable function trace"),
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INIT_PARAM(function_trace_start, "Cycle to start function trace")
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END_INIT_SIM_OBJECT_PARAMS(O3Checker)
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CREATE_SIM_OBJECT(O3Checker)
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{
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O3Checker::Params *params = new O3Checker::Params();
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params->name = getInstanceName();
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params->numberOfThreads = 1;
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params->max_insts_any_thread = 0;
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params->max_insts_all_threads = 0;
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params->max_loads_any_thread = 0;
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params->max_loads_all_threads = 0;
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params->exitOnError = exitOnError;
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params->updateOnError = updateOnError;
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params->deferRegistration = defer_registration;
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params->functionTrace = function_trace;
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params->functionTraceStart = function_trace_start;
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params->clock = clock;
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// Hack to touch all parameters. Consider not deriving Checker
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// from BaseCPU..it's not really a CPU in the end.
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Counter temp;
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temp = max_insts_any_thread;
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temp = max_insts_all_threads;
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temp = max_loads_any_thread;
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temp = max_loads_all_threads;
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Tick temp2 = progress_interval;
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temp2++;
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BaseMem *cache = icache;
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cache = dcache;
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#if FULL_SYSTEM
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params->itb = itb;
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params->dtb = dtb;
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params->mem = mem;
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params->system = system;
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params->cpu_id = cpu_id;
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params->profile = profile;
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#else
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params->process = workload;
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#endif
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O3Checker *cpu = new O3Checker(params);
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return cpu;
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}
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REGISTER_SIM_OBJECT("O3Checker", O3Checker)
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