1097aa1638
This changeset updates the dot output to bail out if it is unable to resolve the voltage or clock domains (which will cause it to raise an AttributeError). Additionally, the DVFS dot output is disabled by default for speed purposes. Minor fixup for 0aeca8f.
393 lines
16 KiB
Python
393 lines
16 KiB
Python
# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Hansson
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# Uri Wiener
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# Sascha Bischoff
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#####################################################################
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#
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# System visualization using DOT
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#
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# While config.ini and config.json provide an almost complete listing
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# of a system's components and connectivity, they lack a birds-eye
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# view. The output generated by do_dot() is a DOT-based figure (as a
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# pdf and an editable svg file) and its source dot code. Nodes are
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# components, and edges represent the memory hierarchy: the edges are
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# directed, from a master to slave. Initially all nodes are
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# generated, and then all edges are added. do_dot should be called
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# with the top-most SimObject (namely root but not necessarily), the
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# output folder and the output dot source filename. From the given
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# node, both processes (node and edge creation) is performed
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# recursivly, traversing all children of the given root.
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#
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# pydot is required. When missing, no output will be generated.
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#
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#####################################################################
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import m5, os, re
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from m5.SimObject import isRoot, isSimObjectVector
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from m5.params import PortRef
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from m5.util import warn
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try:
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import pydot
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except:
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pydot = False
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# need to create all nodes (components) before creating edges (memory channels)
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def dot_create_nodes(simNode, callgraph):
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if isRoot(simNode):
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label = "root"
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else:
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label = simNode._name
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full_path = re.sub('\.', '_', simNode.path())
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# add class name under the label
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label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\""
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# each component is a sub-graph (cluster)
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cluster = dot_create_cluster(simNode, full_path, label)
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# create nodes per port
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for port_name in simNode._ports.keys():
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port = simNode._port_refs.get(port_name, None)
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if port != None:
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full_port_name = full_path + "_" + port_name
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port_node = dot_create_node(simNode, full_port_name, port_name)
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cluster.add_node(port_node)
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# recurse to children
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if simNode._children:
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for c in simNode._children:
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child = simNode._children[c]
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if isSimObjectVector(child):
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for obj in child:
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dot_create_nodes(obj, cluster)
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else:
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dot_create_nodes(child, cluster)
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callgraph.add_subgraph(cluster)
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# create all edges according to memory hierarchy
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def dot_create_edges(simNode, callgraph):
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for port_name in simNode._ports.keys():
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port = simNode._port_refs.get(port_name, None)
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if port != None:
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full_path = re.sub('\.', '_', simNode.path())
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full_port_name = full_path + "_" + port_name
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port_node = dot_create_node(simNode, full_port_name, port_name)
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# create edges
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if isinstance(port, PortRef):
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dot_add_edge(simNode, callgraph, full_port_name, port)
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else:
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for p in port.elements:
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dot_add_edge(simNode, callgraph, full_port_name, p)
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# recurse to children
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if simNode._children:
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for c in simNode._children:
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child = simNode._children[c]
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if isSimObjectVector(child):
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for obj in child:
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dot_create_edges(obj, callgraph)
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else:
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dot_create_edges(child, callgraph)
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def dot_add_edge(simNode, callgraph, full_port_name, peerPort):
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if peerPort.role == "MASTER":
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peer_port_name = re.sub('\.', '_', peerPort.peer.simobj.path() \
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+ "." + peerPort.peer.name)
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callgraph.add_edge(pydot.Edge(full_port_name, peer_port_name))
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def dot_create_cluster(simNode, full_path, label):
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# get the parameter values of the node and use them as a tooltip
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ini_strings = []
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for param in sorted(simNode._params.keys()):
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value = simNode._values.get(param)
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if value != None:
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# parameter name = value in HTML friendly format
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ini_strings.append(str(param) + "=" +
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simNode._values[param].ini_str())
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# join all the parameters with an HTML newline
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tooltip = " ".join(ini_strings)
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return pydot.Cluster( \
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full_path, \
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shape = "Mrecord", \
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label = label, \
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tooltip = "\"" + tooltip + "\"", \
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style = "\"rounded, filled\"", \
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color = "#000000", \
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fillcolor = dot_gen_colour(simNode), \
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fontname = "Arial", \
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fontsize = "14", \
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fontcolor = "#000000" \
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)
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def dot_create_node(simNode, full_path, label):
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return pydot.Node( \
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full_path, \
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shape = "Mrecord", \
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label = label, \
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style = "\"rounded, filled\"", \
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color = "#000000", \
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fillcolor = dot_gen_colour(simNode, True), \
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fontname = "Arial", \
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fontsize = "14", \
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fontcolor = "#000000" \
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)
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# an enumerator for different kinds of node types, at the moment we
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# discern the majority of node types, with the caches being the
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# notable exception
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class NodeType:
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SYS = 0
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CPU = 1
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XBAR = 2
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MEM = 3
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DEV = 4
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OTHER = 5
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# based on the sim object, determine the node type
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def get_node_type(simNode):
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if isinstance(simNode, m5.objects.System):
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return NodeType.SYS
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# NULL ISA has no BaseCPU or PioDevice, so check if these names
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# exists before using them
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elif 'BaseCPU' in dir(m5.objects) and \
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isinstance(simNode, m5.objects.BaseCPU):
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return NodeType.CPU
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elif 'PioDevice' in dir(m5.objects) and \
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isinstance(simNode, m5.objects.PioDevice):
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return NodeType.DEV
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elif isinstance(simNode, m5.objects.BaseXBar):
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return NodeType.XBAR
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elif isinstance(simNode, m5.objects.AbstractMemory):
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return NodeType.MEM
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else:
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return NodeType.OTHER
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# based on the node type, determine the colour as an RGB tuple, the
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# palette is rather arbitrary at this point (some coherent natural
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# tones), and someone that feels artistic should probably have a look
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def get_type_colour(nodeType):
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if nodeType == NodeType.SYS:
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return (228, 231, 235)
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elif nodeType == NodeType.CPU:
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return (187, 198, 217)
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elif nodeType == NodeType.XBAR:
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return (111, 121, 140)
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elif nodeType == NodeType.MEM:
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return (94, 89, 88)
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elif nodeType == NodeType.DEV:
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return (199, 167, 147)
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elif nodeType == NodeType.OTHER:
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# use a relatively gray shade
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return (186, 182, 174)
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# generate colour for a node, either corresponding to a sim object or a
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# port
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def dot_gen_colour(simNode, isPort = False):
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# determine the type of the current node, and also its parent, if
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# the node is not the same type as the parent then we use the base
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# colour for its type
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node_type = get_node_type(simNode)
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if simNode._parent:
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parent_type = get_node_type(simNode._parent)
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else:
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parent_type = NodeType.OTHER
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# if this node is the same type as the parent, then scale the
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# colour based on the depth such that the deeper levels in the
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# hierarchy get darker colours
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if node_type == parent_type:
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# start out with a depth of zero
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depth = 0
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parent = simNode._parent
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# find the closes parent that is not the same type
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while parent and get_node_type(parent) == parent_type:
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depth = depth + 1
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parent = parent._parent
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node_colour = get_type_colour(parent_type)
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# slightly arbitrary, but assume that the depth is less than
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# five levels
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r, g, b = map(lambda x: x * max(1 - depth / 7.0, 0.3), node_colour)
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else:
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node_colour = get_type_colour(node_type)
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r, g, b = node_colour
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# if we are colouring a port, then make it a slightly darker shade
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# than the node that encapsulates it, once again use a magic constant
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if isPort:
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r, g, b = map(lambda x: 0.8 * x, (r, g, b))
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return dot_rgb_to_html(r, g, b)
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def dot_rgb_to_html(r, g, b):
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return "#%.2x%.2x%.2x" % (r, g, b)
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# We need to create all of the clock domains. We abuse the alpha channel to get
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# the correct domain colouring.
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def dot_add_clk_domain(c_dom, v_dom):
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label = "\"" + str(c_dom) + "\ :\ " + str(v_dom) + "\""
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label = re.sub('\.', '_', str(label))
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full_path = re.sub('\.', '_', str(c_dom))
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return pydot.Cluster( \
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full_path, \
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shape = "Mrecord", \
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label = label, \
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style = "\"rounded, filled, dashed\"", \
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color = "#000000", \
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fillcolor = "#AFC8AF8F", \
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fontname = "Arial", \
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fontsize = "14", \
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fontcolor = "#000000" \
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)
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def dot_create_dvfs_nodes(simNode, callgraph, domain=None):
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if isRoot(simNode):
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label = "root"
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else:
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label = simNode._name
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full_path = re.sub('\.', '_', simNode.path())
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# add class name under the label
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label = "\"" + label + " \\n: " + simNode.__class__.__name__ + "\""
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# each component is a sub-graph (cluster)
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cluster = dot_create_cluster(simNode, full_path, label)
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# create nodes per port
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for port_name in simNode._ports.keys():
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port = simNode._port_refs.get(port_name, None)
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if port != None:
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full_port_name = full_path + "_" + port_name
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port_node = dot_create_node(simNode, full_port_name, port_name)
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cluster.add_node(port_node)
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# Dictionary of DVFS domains
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dvfs_domains = {}
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# recurse to children
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if simNode._children:
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for c in simNode._children:
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child = simNode._children[c]
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if isSimObjectVector(child):
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for obj in child:
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try:
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c_dom = obj.__getattr__('clk_domain')
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v_dom = c_dom.__getattr__('voltage_domain')
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except AttributeError:
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# Just re-use the domain from above
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c_dom = domain
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v_dom = c_dom.__getattr__('voltage_domain')
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pass
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if c_dom == domain or c_dom == None:
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dot_create_dvfs_nodes(obj, cluster, domain)
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else:
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if c_dom not in dvfs_domains:
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dvfs_cluster = dot_add_clk_domain(c_dom, v_dom)
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dvfs_domains[c_dom] = dvfs_cluster
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else:
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dvfs_cluster = dvfs_domains[c_dom]
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dot_create_dvfs_nodes(obj, dvfs_cluster, c_dom)
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else:
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try:
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c_dom = child.__getattr__('clk_domain')
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v_dom = c_dom.__getattr__('voltage_domain')
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except AttributeError:
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# Just re-use the domain from above
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c_dom = domain
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v_dom = c_dom.__getattr__('voltage_domain')
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pass
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if c_dom == domain or c_dom == None:
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dot_create_dvfs_nodes(child, cluster, domain)
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else:
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if c_dom not in dvfs_domains:
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dvfs_cluster = dot_add_clk_domain(c_dom, v_dom)
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dvfs_domains[c_dom] = dvfs_cluster
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else:
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dvfs_cluster = dvfs_domains[c_dom]
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dot_create_dvfs_nodes(child, dvfs_cluster, c_dom)
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for key in dvfs_domains:
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cluster.add_subgraph(dvfs_domains[key])
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callgraph.add_subgraph(cluster)
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def do_dot(root, outdir, dotFilename):
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if not pydot:
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return
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# * use ranksep > 1.0 for for vertical separation between nodes
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# especially useful if you need to annotate edges using e.g. visio
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# which accepts svg format
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# * no need for hoizontal separation as nothing moves horizonally
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callgraph = pydot.Dot(graph_type='digraph', ranksep='1.3')
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dot_create_nodes(root, callgraph)
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dot_create_edges(root, callgraph)
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dot_filename = os.path.join(outdir, dotFilename)
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callgraph.write(dot_filename)
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try:
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# dot crashes if the figure is extremely wide.
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# So avoid terminating simulation unnecessarily
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callgraph.write_svg(dot_filename + ".svg")
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callgraph.write_pdf(dot_filename + ".pdf")
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except:
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warn("failed to generate dot output from %s", dot_filename)
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def do_dvfs_dot(root, outdir, dotFilename):
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if not pydot:
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return
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# There is a chance that we are unable to resolve the clock or
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# voltage domains. If so, we fail silently.
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try:
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dvfsgraph = pydot.Dot(graph_type='digraph', ranksep='1.3')
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dot_create_dvfs_nodes(root, dvfsgraph)
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dot_create_edges(root, dvfsgraph)
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dot_filename = os.path.join(outdir, dotFilename)
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dvfsgraph.write(dot_filename)
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except:
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warn("Failed to generate dot graph for DVFS domains")
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return
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try:
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# dot crashes if the figure is extremely wide.
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# So avoid terminating simulation unnecessarily
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dvfsgraph.write_svg(dot_filename + ".svg")
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dvfsgraph.write_pdf(dot_filename + ".pdf")
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except:
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warn("failed to generate dot output from %s", dot_filename)
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