0d32940711
This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. --HG-- rename : src/mem/bus.cc => src/mem/coherent_bus.cc rename : src/mem/bus.hh => src/mem/coherent_bus.hh rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh
200 lines
7.3 KiB
Python
200 lines
7.3 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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import optparse
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import sys
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import m5
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from m5.objects import *
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parser = optparse.OptionParser()
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parser.add_option("-a", "--atomic", action="store_true",
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help="Use atomic (non-timing) mode")
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parser.add_option("-b", "--blocking", action="store_true",
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help="Use blocking caches")
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parser.add_option("-l", "--maxloads", metavar="N", default=0,
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help="Stop after N loads")
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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metavar="T",
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help="Stop after T ticks")
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#
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# The "tree" specification is a colon-separated list of one or more
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# integers. The first integer is the number of caches/testers
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# connected directly to main memory. The last integer in the list is
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# the number of testers associated with the uppermost level of memory
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# (L1 cache, if there are caches, or main memory if no caches). Thus
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# if there is only one integer, there are no caches, and the integer
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# specifies the number of testers connected directly to main memory.
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# The other integers (if any) specify the number of caches at each
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# level of the hierarchy between.
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#
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# Examples:
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#
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# "2:1" Two caches connected to memory with a single tester behind each
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# (single-level hierarchy, two testers total)
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#
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# "2:2:1" Two-level hierarchy, 2 L1s behind each of 2 L2s, 4 testers total
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#
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parser.add_option("-t", "--treespec", type="string", default="8:1",
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help="Colon-separated multilevel tree specification, "
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"see script comments for details "
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"[default: %default]")
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parser.add_option("--force-bus", action="store_true",
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help="Use bus between levels even with single cache")
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parser.add_option("-f", "--functional", type="int", default=0,
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metavar="PCT",
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help="Target percentage of functional accesses "
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"[default: %default]")
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parser.add_option("-u", "--uncacheable", type="int", default=0,
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metavar="PCT",
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help="Target percentage of uncacheable accesses "
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"[default: %default]")
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parser.add_option("--progress", type="int", default=1000,
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metavar="NLOADS",
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help="Progress message interval "
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"[default: %default]")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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block_size = 64
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try:
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treespec = [int(x) for x in options.treespec.split(':')]
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numtesters = reduce(lambda x,y: x*y, treespec)
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except:
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print "Error parsing treespec option"
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sys.exit(1)
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if numtesters > block_size:
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print "Error: Number of testers limited to %s because of false sharing" \
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% (block_size)
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sys.exit(1)
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if len(treespec) < 1:
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print "Error parsing treespec"
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sys.exit(1)
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# define prototype L1 cache
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proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
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latency = '1ns', tgts_per_mshr = 8)
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if options.blocking:
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proto_l1.mshrs = 1
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else:
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proto_l1.mshrs = 4
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# build a list of prototypes, one for each level of treespec, starting
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# at the end (last entry is tester objects)
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prototypes = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
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percent_functional=options.functional,
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percent_uncacheable=options.uncacheable,
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progress_interval=options.progress) ]
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# next comes L1 cache, if any
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if len(treespec) > 1:
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prototypes.insert(0, proto_l1)
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# now add additional cache levels (if any) by scaling L1 params
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for scale in treespec[:-2]:
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# clone previous level and update params
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prev = prototypes[0]
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next = prev()
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next.size = prev.size * scale
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next.latency = prev.latency * 10
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next.assoc = prev.assoc * scale
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next.mshrs = prev.mshrs * scale
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prototypes.insert(0, next)
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# system simulated
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system = System(funcmem = SimpleMemory(in_addr_map = False),
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physmem = SimpleMemory(latency = "100ns"))
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def make_level(spec, prototypes, attach_obj, attach_port):
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fanout = spec[0]
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parent = attach_obj # use attach obj as config parent too
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if len(spec) > 1 and (fanout > 1 or options.force_bus):
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port = getattr(attach_obj, attach_port)
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new_bus = CoherentBus(clock="500MHz", width=16)
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if (port.role == 'MASTER'):
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new_bus.slave = port
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attach_port = "master"
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else:
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new_bus.master = port
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attach_port = "slave"
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parent.cpu_side_bus = new_bus
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attach_obj = new_bus
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objs = [prototypes[0]() for i in xrange(fanout)]
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if len(spec) > 1:
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# we just built caches, more levels to go
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parent.cache = objs
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for cache in objs:
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cache.mem_side = getattr(attach_obj, attach_port)
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make_level(spec[1:], prototypes[1:], cache, "cpu_side")
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else:
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# we just built the MemTest objects
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parent.cpu = objs
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for t in objs:
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t.test = getattr(attach_obj, attach_port)
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t.functional = system.funcmem.port
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make_level(treespec, prototypes, system.physmem, "port")
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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if options.atomic:
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root.system.mem_mode = 'atomic'
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else:
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root.system.mem_mode = 'timing'
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# The system port is never used in the tester so merely connect it
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# to avoid problems
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root.system.system_port = root.system.physmem.port
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(options.maxtick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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