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checker
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TLB: Make a TLB base class and put a virtual demapPage function in it.
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2008-02-26 23:38:51 -05:00 |
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memtest
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Don't FastAlloc MSHRs since we don't allocate them on the fly.
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2008-03-24 01:08:02 -04:00 |
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o3
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Don't FastAlloc MSHRs since we don't allocate them on the fly.
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2008-03-24 01:08:02 -04:00 |
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ozone
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Don't FastAlloc MSHRs since we don't allocate them on the fly.
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2008-03-24 01:08:02 -04:00 |
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simple
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CPU: Make the simple cpu trace data for loads/stores.
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2008-06-12 00:35:50 -04:00 |
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trace
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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activity.cc
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make our code a little more standards compliant
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2007-01-26 18:48:51 -05:00 |
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activity.hh
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Update copyright.
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2006-06-07 16:02:55 -04:00 |
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base.cc
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port: Clean up default port setup and port switchover code.
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2008-06-15 21:34:32 -07:00 |
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base.hh
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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base_dyn_inst.hh
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TLB: Make a TLB base class and put a virtual demapPage function in it.
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2008-02-26 23:38:51 -05:00 |
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base_dyn_inst_impl.hh
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O3CPU: Don't call dumpInsts if DEBUG is not defined
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2008-03-06 00:27:09 -05:00 |
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BaseCPU.py
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Add base ARM code to M5
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2008-02-05 23:44:13 -05:00 |
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cpu_models.py
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Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
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2006-07-06 12:18:55 -04:00 |
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cpuevent.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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cpuevent.hh
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Make SPARC checkpointing work
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2007-01-30 18:25:39 -05:00 |
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exec_context.hh
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*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
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2007-03-07 15:04:31 -05:00 |
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exetrace.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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exetrace.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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ExeTracer.py
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Turn the instruction tracing code into pluggable sim objects.
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2007-07-28 20:30:43 -07:00 |
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func_unit.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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func_unit.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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FuncUnit.py
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Rename enum from OpType to OpClass so it's consistent with the
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2007-06-11 23:10:58 -07:00 |
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inst_seq.hh
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fixes so that M5 will compile under solaris
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2006-11-04 21:41:01 -05:00 |
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inteltrace.cc
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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inteltrace.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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IntelTrace.py
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Turn the instruction tracing code into pluggable sim objects.
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2007-07-28 20:30:43 -07:00 |
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intr_control.cc
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Interrupts: Inline some code and remove duplication.
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2007-11-08 10:46:41 -05:00 |
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intr_control.hh
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Interrupts: Inline some code and remove duplication.
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2007-11-08 10:46:41 -05:00 |
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IntrControl.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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legiontrace.cc
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String constant const-ness changes to placate g++ 4.2.
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2007-10-31 18:04:22 -07:00 |
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legiontrace.hh
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params: Deprecate old-style constructors; update most SimObject constructors.
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2007-08-30 15:16:59 -04:00 |
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LegionTrace.py
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Turn the instruction tracing code into pluggable sim objects.
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2007-07-28 20:30:43 -07:00 |
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m5legion_interface.h
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add fsr to the list of registers we are interested in
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2007-01-30 18:27:04 -05:00 |
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nativetrace.cc
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X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm.
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2007-09-04 23:39:57 -07:00 |
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nativetrace.hh
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X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm.
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2007-09-04 23:39:57 -07:00 |
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NativeTrace.py
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Turn the instruction tracing code into pluggable sim objects.
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2007-07-28 20:30:43 -07:00 |
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op_class.hh
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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pc_event.cc
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remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault
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2007-03-12 17:23:08 -04:00 |
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pc_event.hh
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Added sim/host.hh for the Addr type.
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2006-11-07 05:42:15 -05:00 |
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profile.cc
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Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
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2006-06-06 17:32:21 -04:00 |
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profile.hh
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Put the ProcessInfo and StackTrace objects into the ISA namespaces.
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2006-11-08 00:52:04 -05:00 |
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quiesce_event.cc
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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quiesce_event.hh
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Make the Event::description() a const function
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2008-02-06 16:32:40 -05:00 |
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SConscript
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SCons: add comments to SConscript documenting bug workaround
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2008-04-10 15:38:10 -04:00 |
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simple_thread.cc
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Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
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2007-08-26 20:24:18 -07:00 |
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simple_thread.hh
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TLB: Make a TLB base class and put a virtual demapPage function in it.
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2008-02-26 23:38:51 -05:00 |
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smt.hh
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Updated Authors from bk prs info
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2006-05-31 19:26:56 -04:00 |
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static_inst.cc
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Modified instruction decode method.
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2007-06-14 16:52:19 -04:00 |
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static_inst.hh
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Add base ARM code to M5
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2008-02-05 23:44:13 -05:00 |
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thread_context.cc
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CPU: Add function to explictly compare thread contexts after copying.
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2007-11-08 10:46:41 -05:00 |
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thread_context.hh
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add MicroPC functions back to thread context
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2007-11-15 20:35:31 -05:00 |
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thread_state.cc
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fix the translating ports so it can add a page on a fault
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2007-05-09 15:37:46 -04:00 |
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thread_state.hh
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Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
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2006-11-29 16:07:55 -05:00 |
