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gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.233283 # Number of seconds simulated
sim_ticks 233282768000 # Number of ticks simulated
final_tick 233282768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 136250 # Simulator instruction rate (inst/s)
host_op_rate 147606 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 62910352 # Simulator tick rate (ticks/s)
host_mem_usage 320784 # Number of bytes of host memory used
host_seconds 3708.18 # Real time elapsed on the host
sim_insts 505237724 # Number of instructions simulated
sim_ops 547350945 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 683136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9221056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 16463744 # Number of bytes read from this memory
system.physmem.bytes_read::total 26367936 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 683136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 683136 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18705728 # Number of bytes written to this memory
system.physmem.bytes_written::total 18705728 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 10674 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 144079 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 257246 # Number of read requests responded to by this memory
system.physmem.num_reads::total 411999 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 292277 # Number of write requests responded to by this memory
system.physmem.num_writes::total 292277 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2928360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39527377 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 70574197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 113029935 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2928360 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2928360 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 80184782 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 80184782 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 80184782 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2928360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39527377 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 70574197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 193214717 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 411999 # Number of read requests accepted
system.physmem.writeReqs 292277 # Number of write requests accepted
system.physmem.readBursts 411999 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 292277 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26229824 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 138112 # Total number of bytes read from write queue
system.physmem.bytesWritten 18703872 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26367936 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18705728 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 2158 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 26728 # Per bank write bursts
system.physmem.perBankRdBursts::1 25477 # Per bank write bursts
system.physmem.perBankRdBursts::2 25253 # Per bank write bursts
system.physmem.perBankRdBursts::3 24678 # Per bank write bursts
system.physmem.perBankRdBursts::4 27151 # Per bank write bursts
system.physmem.perBankRdBursts::5 26546 # Per bank write bursts
system.physmem.perBankRdBursts::6 25195 # Per bank write bursts
system.physmem.perBankRdBursts::7 24195 # Per bank write bursts
system.physmem.perBankRdBursts::8 25840 # Per bank write bursts
system.physmem.perBankRdBursts::9 24882 # Per bank write bursts
system.physmem.perBankRdBursts::10 24886 # Per bank write bursts
system.physmem.perBankRdBursts::11 26093 # Per bank write bursts
system.physmem.perBankRdBursts::12 26302 # Per bank write bursts
system.physmem.perBankRdBursts::13 26067 # Per bank write bursts
system.physmem.perBankRdBursts::14 24895 # Per bank write bursts
system.physmem.perBankRdBursts::15 25653 # Per bank write bursts
system.physmem.perBankWrBursts::0 18973 # Per bank write bursts
system.physmem.perBankWrBursts::1 18287 # Per bank write bursts
system.physmem.perBankWrBursts::2 17868 # Per bank write bursts
system.physmem.perBankWrBursts::3 17935 # Per bank write bursts
system.physmem.perBankWrBursts::4 18795 # Per bank write bursts
system.physmem.perBankWrBursts::5 18319 # Per bank write bursts
system.physmem.perBankWrBursts::6 17931 # Per bank write bursts
system.physmem.perBankWrBursts::7 17655 # Per bank write bursts
system.physmem.perBankWrBursts::8 18179 # Per bank write bursts
system.physmem.perBankWrBursts::9 17927 # Per bank write bursts
system.physmem.perBankWrBursts::10 17987 # Per bank write bursts
system.physmem.perBankWrBursts::11 18662 # Per bank write bursts
system.physmem.perBankWrBursts::12 18697 # Per bank write bursts
system.physmem.perBankWrBursts::13 18344 # Per bank write bursts
system.physmem.perBankWrBursts::14 18231 # Per bank write bursts
system.physmem.perBankWrBursts::15 18458 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 233282750000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 411999 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 292277 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 312898 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 47873 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13110 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7330 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 6176 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 5273 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 4418 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3450 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 96 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6395 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6689 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 13204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 15353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 16370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 16918 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17443 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17610 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17839 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 18048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 18366 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 18616 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 18818 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 19964 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 18185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17459 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 306889 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 146.413224 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 102.997180 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 182.093051 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 184151 60.01% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 82036 26.73% 86.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 16582 5.40% 92.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7394 2.41% 94.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4756 1.55% 96.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2254 0.73% 96.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1661 0.54% 97.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1625 0.53% 97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6430 2.10% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 306889 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17312 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.673001 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 116.829793 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 17311 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 17312 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17312 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.881238 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.838780 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.240848 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 10485 60.56% 60.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 306 1.77% 62.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 5502 31.78% 94.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 671 3.88% 97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 134 0.77% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 74 0.43% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 42 0.24% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 45 0.26% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 29 0.17% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 14 0.08% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 9 0.05% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17312 # Writes before turning the bus around for reads
system.physmem.totQLat 9036310212 # Total ticks spent queuing
system.physmem.totMemAccLat 16720828962 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2049205000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22048.33 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 40798.33 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 112.44 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 80.18 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 113.03 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 80.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.50 # Data bus utilization in percentage
system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.78 # Average write queue length when enqueuing
system.physmem.readRowHits 299552 # Number of row buffer hits during reads
system.physmem.writeRowHits 95641 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
system.physmem.avgGap 331237.68 # Average gap between requests
system.physmem.pageHitRate 56.29 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1156763160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 631170375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1600435200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 944401680 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 74473770375 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 74637909000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 168680907390 # Total energy per rank (pJ)
system.physmem_0.averagePower 723.094931 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 123643637069 # Time in different power states
system.physmem_0.memoryStateTime::REF 7789600000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 101845250931 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 1163007720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 634577625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1595802000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 949158000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 74040443550 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 75018020250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 168637466745 # Total energy per rank (pJ)
system.physmem_1.averagePower 722.908711 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 124281047938 # Time in different power states
system.physmem_1.memoryStateTime::REF 7789600000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 101208398062 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 175089811 # Number of BP lookups
system.cpu.branchPred.condPredicted 131337021 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 7444155 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 90376647 # Number of BTB lookups
system.cpu.branchPred.BTBHits 83876100 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.807271 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 12110019 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 104160 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 466565537 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7838065 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 731795546 # Number of instructions fetch has processed
system.cpu.fetch.Branches 175089811 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 95986119 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 450385778 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 14940817 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 5837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 14677 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 236716672 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 34578 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 465715008 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.701748 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.179403 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 93791115 20.14% 20.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 132693411 28.49% 48.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 57855471 12.42% 61.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 181375011 38.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 465715008 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.375274 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.568473 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 32367511 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 117249871 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 287084329 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 22031549 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 6981748 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 24050134 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 496459 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 715800999 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 30008433 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 6981748 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 63425626 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 54212557 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 40336788 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 276681526 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 24076763 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 686589929 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 13340569 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 9410638 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2384158 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1669115 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 1841927 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 831018421 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3019159141 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 723918647 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 176894670 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1544698 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1534992 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 42289780 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 143526215 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 67981217 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12855514 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11197113 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 668159255 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2978326 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 610231748 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5860169 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 123786636 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 319274742 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 465715008 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.310312 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.101358 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 148574576 31.90% 31.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 101171602 21.72% 53.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 145766544 31.30% 84.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 63282576 13.59% 98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6919220 1.49% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 490 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 465715008 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 71921517 52.96% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44556516 32.81% 85.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 19328890 14.23% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 413144323 67.70% 67.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 351745 0.06% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 134209580 21.99% 89.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 62526097 10.25% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 610231748 # Type of FU issued
system.cpu.iq.rate 1.307923 # Inst issue rate
system.cpu.iq.fu_busy_cnt 135806953 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.222550 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1827845333 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 794952356 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 594966802 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 746038524 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 7273046 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 27641459 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 25471 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 28891 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 11120740 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 225190 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 22470 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 6981748 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23001930 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 919984 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 672625014 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 143526215 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 67981217 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1489784 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 258650 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 525178 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 28891 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3821630 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3731398 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 7553028 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 599382547 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 129570228 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10849201 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1487433 # number of nop insts executed
system.cpu.iew.exec_refs 190523509 # number of memory reference insts executed
system.cpu.iew.exec_branches 131370037 # Number of branches executed
system.cpu.iew.exec_stores 60953281 # Number of stores executed
system.cpu.iew.exec_rate 1.284670 # Inst execution rate
system.cpu.iew.wb_sent 596261681 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 594966818 # cumulative count of insts written-back
system.cpu.iew.wb_producers 349901968 # num instructions producing a value
system.cpu.iew.wb_consumers 570648646 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.275205 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.613165 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 110016162 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 6955495 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 448601420 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.223123 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.887905 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 219539851 48.94% 48.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 116349885 25.94% 74.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43748468 9.75% 84.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 23302371 5.19% 89.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11552802 2.58% 92.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7777273 1.73% 94.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8275373 1.84% 95.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4252092 0.95% 96.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13803305 3.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 448601420 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581608 # Number of instructions committed
system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 172745233 # Number of memory references committed
system.cpu.commit.loads 115884756 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 121548302 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction
system.cpu.commit.bw_lim_events 13803305 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 1093501968 # The number of ROB reads
system.cpu.rob.rob_writes 1334565325 # The number of ROB writes
system.cpu.timesIdled 13884 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 850529 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237724 # Number of Instructions Simulated
system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.923457 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.923457 # CPI: Total CPI of All Threads
system.cpu.ipc 1.082887 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.082887 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 611072880 # number of integer regfile reads
system.cpu.int_regfile_writes 328111730 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.cc_regfile_reads 2170116632 # number of cc regfile reads
system.cpu.cc_regfile_writes 376537008 # number of cc regfile writes
system.cpu.misc_regfile_reads 217962216 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
system.cpu.dcache.tags.replacements 2820796 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.631791 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 169351038 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2821308 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 60.025718 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 498038000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.631791 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 356237372 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 356237372 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114646487 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114646487 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 51724617 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 51724617 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 166371104 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 166371104 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 166373887 # number of overall hits
system.cpu.dcache.overall_hits::total 166373887 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4842277 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4842277 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2514689 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2514689 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 7356966 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7356966 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7356978 # number of overall misses
system.cpu.dcache.overall_misses::total 7356978 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 56244825000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 56244825000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18846227941 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18846227941 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1242500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 1242500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75091052941 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75091052941 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75091052941 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75091052941 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 119488764 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 119488764 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 173728070 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 173728070 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 173730865 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 173730865 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040525 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040525 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046363 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.046363 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.042348 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.042348 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.042347 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.042347 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7494.456746 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 7494.456746 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10206.796245 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10206.779596 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 911242 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 221024 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.500000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 4.122819 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2356243 # number of writebacks
system.cpu.dcache.writebacks::total 2356243 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540565 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2540565 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995076 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1995076 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4535641 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4535641 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4535641 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4535641 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301712 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 2301712 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2821325 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2821325 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2821335 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2821335 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28710026000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 28710026000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4575255494 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4575255494 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 657000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 657000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33285281494 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 33285281494 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33285938494 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 33285938494 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8805.121300 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8805.121300 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65700 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65700 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 73477 # number of replacements
system.cpu.icache.tags.tagsinuse 466.193561 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 236634038 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 73989 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3198.232683 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 114977932500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 466.193561 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.910534 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.910534 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 473507120 # Number of tag accesses
system.cpu.icache.tags.data_accesses 473507120 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 236634038 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 236634038 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 236634038 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 236634038 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 236634038 # number of overall hits
system.cpu.icache.overall_hits::total 236634038 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 82514 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 82514 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 82514 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 82514 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 82514 # number of overall misses
system.cpu.icache.overall_misses::total 82514 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1544948153 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1544948153 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1544948153 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1544948153 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1544948153 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1544948153 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 236716552 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 236716552 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 236716552 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 236716552 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 236716552 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 236716552 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18723.466963 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18723.466963 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18723.466963 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18723.466963 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 193180 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6947 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 27.807687 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8497 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 8497 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 8497 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 8497 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 8497 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 8497 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74017 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 74017 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 74017 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 74017 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 74017 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 74017 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1266772756 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1266772756 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1266772756 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1266772756 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1266772756 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1266772756 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.619020 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17114.619020 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 8510429 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 8512950 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 1055 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 742850 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 400878 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15418.113154 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 5066482 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 417216 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 12.143547 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 34592827000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8451.219479 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 476.205325 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 4934.937237 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1555.751112 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.515822 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029065 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.301205 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094956 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.941047 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1092 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15246 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 37 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 235 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 819 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1560 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9946 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3385 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066650 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930542 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 93192221 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 93192221 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 2356243 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2356243 # number of Writeback hits
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system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63301 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 63301 # number of ReadCleanReq hits
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system.cpu.l2cache.overall_hits::cpu.data 2671464 # number of overall hits
system.cpu.l2cache.overall_hits::total 2734765 # number of overall hits
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system.cpu.l2cache.ReadExReq_misses::total 5205 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10683 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 10683 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 144639 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 144639 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 10683 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::total 160527 # number of overall misses
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system.cpu.l2cache.overall_miss_latency::cpu.data 11608288000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12388069500 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 2356243 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2356243 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.144396 # miss rate for ReadCleanReq accesses
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system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144396 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144396 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.053112 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.055444 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88455.907781 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88455.907781 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72992.745483 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72992.745483 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77073.783696 # average ReadSharedReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72992.745483 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77469.154587 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 292277 # number of writebacks
system.cpu.l2cache.writebacks::total 292277 # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1529 # number of ReadExReq MSHR hits
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system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4235 # number of ReadSharedReq MSHR hits
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system.cpu.l2cache.demand_mshr_hits::cpu.data 5764 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits::cpu.data 5764 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5772 # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6839 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 6839 # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 274923 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 274923 # number of HardPFReq MSHR misses
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10269035500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 30101606245 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007043 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007043 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144288 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.061063 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.061063 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.053451 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.148406 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp 2373352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2648520 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 622852 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 320716 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 521972 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 521972 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 74017 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299336 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220623 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440541 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8661164 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734912 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331363264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 336098176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 721627 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6511219 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.110823 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.313913 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5789625 88.92% 88.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 721594 11.08% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6511219 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5251055500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 111049948 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 4231992466 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
system.membus.trans_dist::ReadResp 408324 # Transaction distribution
system.membus.trans_dist::Writeback 292277 # Transaction distribution
system.membus.trans_dist::CleanEvict 103036 # Transaction distribution
system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 3675 # Transaction distribution
system.membus.trans_dist::ReadExResp 3675 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 408324 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219317 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1219317 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45073664 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 45073664 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 807315 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 807315 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 807315 # Request fanout histogram
system.membus.reqLayer0.occupancy 2175050688 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2177979128 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
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