25e1b1c1f5
This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
1006 lines
115 KiB
Plaintext
1006 lines
115 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.062104 # Number of seconds simulated
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sim_ticks 62103992500 # Number of ticks simulated
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final_tick 62103992500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 108853 # Simulator instruction rate (inst/s)
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host_op_rate 191673 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 42789284 # Simulator tick rate (ticks/s)
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host_mem_usage 455804 # Number of bytes of host memory used
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host_seconds 1451.39 # Real time elapsed on the host
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sim_insts 157988547 # Number of instructions simulated
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sim_ops 278192464 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1883648 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1948480 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory
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system.physmem.bytes_written::total 11776 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 29432 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 30445 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 184 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1043926 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 30330546 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 31374472 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1043926 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1043926 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 189617 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 189617 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 189617 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1043926 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 30330546 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 31564090 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 30446 # Number of read requests accepted
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system.physmem.writeReqs 184 # Number of write requests accepted
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system.physmem.readBursts 30446 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 1943488 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue
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system.physmem.bytesWritten 10368 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 1948544 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 1927 # Per bank write bursts
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system.physmem.perBankRdBursts::1 2069 # Per bank write bursts
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system.physmem.perBankRdBursts::2 2026 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1929 # Per bank write bursts
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system.physmem.perBankRdBursts::4 2026 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1901 # Per bank write bursts
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system.physmem.perBankRdBursts::6 1959 # Per bank write bursts
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system.physmem.perBankRdBursts::7 1865 # Per bank write bursts
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system.physmem.perBankRdBursts::8 1938 # Per bank write bursts
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system.physmem.perBankRdBursts::9 1937 # Per bank write bursts
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system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
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system.physmem.perBankRdBursts::11 1796 # Per bank write bursts
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system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
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system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
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system.physmem.perBankRdBursts::14 1819 # Per bank write bursts
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system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
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system.physmem.perBankWrBursts::0 25 # Per bank write bursts
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system.physmem.perBankWrBursts::1 94 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 13 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5 # Per bank write bursts
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system.physmem.perBankWrBursts::10 3 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 62103972000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 30446 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 184 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 29885 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 384 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 2720 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 718.117647 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 516.851204 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 389.329010 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 349 12.83% 12.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 252 9.26% 22.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 126 4.63% 26.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 106 3.90% 30.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 106 3.90% 34.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 118 4.34% 38.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 88 3.24% 42.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 74 2.72% 44.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 1501 55.18% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 2720 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 3367.333333 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 25.147360 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 10062.626521 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 9 100.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
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system.physmem.totQLat 131808750 # Total ticks spent queuing
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system.physmem.totMemAccLat 701190000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 151835000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 4340.53 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 23090.53 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 31.38 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.25 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 13.82 # Average write queue length when enqueuing
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system.physmem.readRowHits 27697 # Number of row buffer hits during reads
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system.physmem.writeRowHits 108 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 58.70 # Row buffer hit rate for writes
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system.physmem.avgGap 2027553.77 # Average gap between requests
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system.physmem.pageHitRate 91.01 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 10848600 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 5919375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 122421000 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 997920 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2874471525 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 34740567750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 41811500730 # Total energy per rank (pJ)
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system.physmem_0.averagePower 673.256335 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 57777967000 # Time in different power states
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system.physmem_0.memoryStateTime::REF 2073760000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 2251676750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 114371400 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 3081237030 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 34559194500 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 41826144555 # Total energy per rank (pJ)
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system.physmem_1.averagePower 673.492132 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 57475856750 # Time in different power states
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system.physmem_1.memoryStateTime::REF 2073760000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 2554341750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 37407153 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 37407153 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 797525 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 21397569 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 21291133 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 99.502579 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 5522199 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 5378 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
system.cpu.workload.num_syscalls 444 # Number of system calls
|
|
system.cpu.numCycles 124207986 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 28243826 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 201531916 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 37407153 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 26813332 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 95053081 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1666271 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 3 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 14570 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.CacheLines 27854872 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 208775 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 124145503 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.860655 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.369153 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 63227150 50.93% 50.93% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 3664165 2.95% 53.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 3505505 2.82% 56.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 5966108 4.81% 61.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 7642313 6.16% 67.67% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 5450974 4.39% 72.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 3347715 2.70% 74.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 2079081 1.67% 76.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 29262492 23.57% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 124145503 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.301165 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.622536 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 13298609 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 63688691 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 36532978 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9792090 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 833135 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 335053232 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 833135 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 18606460 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 8830273 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 16174 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 40807487 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 55051974 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 328692220 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 2265 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 765831 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 48323645 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 4961410 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 330669691 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 873156420 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 537756143 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 567 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 51456944 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 481 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 66169497 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 106330183 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 36531613 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 49817317 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 8395275 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 325507363 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2500 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 308019505 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 50533 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 47317399 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 68952386 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2055 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 124145503 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.481117 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.143684 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 30872061 24.87% 24.87% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 19525697 15.73% 40.60% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 16787256 13.52% 54.12% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 17357634 13.98% 68.10% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 14846406 11.96% 80.06% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 12689504 10.22% 90.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 6302474 5.08% 95.36% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 3917362 3.16% 98.51% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1847109 1.49% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 124145503 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 329941 8.31% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.31% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 3456308 87.04% 95.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 184474 4.65% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 175410718 56.95% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 11212 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 340 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 98529790 31.99% 88.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 34034069 11.05% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 308019505 # Type of FU issued
|
|
system.cpu.iq.rate 2.479869 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 3970723 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.012891 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 744205245 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 372866875 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 306008038 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 524 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 864 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 311956642 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 248 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 58273942 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 15550798 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 67136 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 41716 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 5091861 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3678 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 142532 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 833135 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 5706209 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 3030570 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 325509863 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 125935 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 106330183 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 36531613 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 471 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2800 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3033928 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 41716 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 402612 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 445047 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 847659 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 306958421 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 98183223 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1061084 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 132003276 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 31537655 # Number of branches executed
|
|
system.cpu.iew.exec_stores 33820053 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.471326 # Inst execution rate
|
|
system.cpu.iew.wb_sent 306335531 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 306008206 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 231609196 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 336109097 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.463676 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.689089 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 47420049 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 798401 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 117693042 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.363712 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 3.086908 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 53351319 45.33% 45.33% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 15952359 13.55% 58.89% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 10962553 9.31% 68.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 8763534 7.45% 75.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1923790 1.63% 77.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1729278 1.47% 78.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 853123 0.72% 79.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 692579 0.59% 80.06% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 23464507 19.94% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 117693042 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
|
|
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 122219137 # Number of memory references committed
|
|
system.cpu.commit.loads 90779385 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 29309705 # Number of branches committed
|
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 4237596 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 23464507 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 419841048 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 657686557 # The number of ROB writes
|
|
system.cpu.timesIdled 566 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 62483 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
|
|
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.786183 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.786183 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.271968 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.271968 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 493729388 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 240917610 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 146 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 96 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 107705980 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 64576396 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 196329384 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2072430 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4068.090496 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 68424035 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2076526 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 32.951206 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 19739908500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4068.090496 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.993186 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.993186 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3373 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 144493228 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 144493228 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 37078222 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 37078222 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 31345813 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 31345813 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 68424035 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 68424035 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 68424035 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 68424035 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2690377 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2690377 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 93939 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 93939 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2784316 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2784316 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2784316 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2784316 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32316565000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 32316565000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2955969494 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2955969494 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 35272534494 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 35272534494 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 35272534494 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 35272534494 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 39768599 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 39768599 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 71208351 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 71208351 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 71208351 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 71208351 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067651 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.067651 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.039101 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.039101 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.039101 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.039101 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 12668.294293 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 12668.294293 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 221313 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 43094 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135587 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2066711 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2066711 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 695911 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 695911 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11877 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 11877 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 707788 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 707788 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 707788 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 707788 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994466 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1994466 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82062 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2076528 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2076528 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2076528 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2076528 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24203306500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24203306500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2798613994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2798613994 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27001920494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 27001920494 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27001920494 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 27001920494 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050152 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 64 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 833.320748 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 27853507 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1032 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 26989.832364 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 833.320748 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.406895 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.406895 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 968 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.472656 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 55710776 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 55710776 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 27853507 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 27853507 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 27853507 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 27853507 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 27853507 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 27853507 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1365 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1365 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1365 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1365 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1365 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1365 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 98783500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 98783500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 98783500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 98783500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 98783500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 98783500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 27854872 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 27854872 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 27854872 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 27854872 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 27854872 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 27854872 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72368.864469 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 72368.864469 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72368.864469 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 72368.864469 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72368.864469 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 72368.864469 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 72.333333 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 333 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 333 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 333 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 333 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 333 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1032 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1032 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1032 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1032 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 78148000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 78148000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 78148000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 78148000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 78148000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 78148000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.806202 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.806202 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.806202 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.806202 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.806202 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.806202 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 495 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 20681.782708 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4035350 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 30428 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 132.619627 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 19745.210929 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 683.118816 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 253.452964 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.602576 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020847 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007735 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.631158 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29933 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 776 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1394 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27641 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913483 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 33312880 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 33312880 # Number of data accesses
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2066711 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2066711 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 53096 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 53096 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 19 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 19 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1993999 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 1993999 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2047095 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2047114 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2047095 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2047114 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1013 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 1013 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 437 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 437 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1013 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 29433 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 30446 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1013 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 29433 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 30446 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2117372000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2117372000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 76394500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 76394500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33330500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 33330500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 76394500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2150702500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 2227097000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 76394500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2150702500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 2227097000 # number of overall miss cycles
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2066711 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2066711 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82092 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 82092 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994436 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1994436 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2076528 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2077560 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2076528 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2077560 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353213 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.353213 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.981589 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.981589 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000219 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000219 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.981589 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014174 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014655 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.981589 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014174 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014655 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73022.899710 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73022.899710 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75414.116486 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75414.116486 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76271.167048 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76271.167048 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75414.116486 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.127646 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 73149.083623 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75414.116486 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.127646 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 73149.083623 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 184 # number of writebacks
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1013 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1013 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 437 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 437 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1013 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 29433 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 30446 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1013 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 29433 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 30446 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827412000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827412000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66264500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66264500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28980500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28980500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66264500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856392500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1922657000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66264500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856392500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1922657000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353213 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353213 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.981589 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000219 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000219 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014174 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014655 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014174 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014655 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63022.899710 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63022.899710 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65414.116486 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65414.116486 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66316.933638 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66316.933638 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65414.116486 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63071.807155 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63149.740524 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65414.116486 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63071.807155 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63149.740524 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1995466 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2066895 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 6085 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 82092 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 82092 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1032 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994436 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2128 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225475 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 6227603 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265167168 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 265233216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 495 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4150549 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.010920 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 4150054 99.99% 99.99% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 495 0.01% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 4150549 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4141738000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1548000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3114789000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 1448 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 184 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 34 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 28996 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 28996 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 1450 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61108 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61108 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 61108 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1960192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1960192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 1960192 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 30664 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 30664 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 42854000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 160427250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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