6fa936b021
Previous ARM-based simulations were limited to 8 cores due to limitations in GICv2 and earlier. This changeset adds a set of gem5-specific extensions that enable support for up to 256 cores. When the gem5 extensions are enabled, the GIC uses CPU IDs instead of a CPU bitmask in the GIC's register interface. To OS can enable the extensions by setting bit 0x200 in ICDICTR. This changeset is based on previous work by Matt Evans.
338 lines
12 KiB
C++
338 lines
12 KiB
C++
/*
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* Copyright (c) 2010, 2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/** @file
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* Implementiation of a PL390 GIC
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*/
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#ifndef __DEV_ARM_GIC_PL390_H__
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#define __DEV_ARM_GIC_PL390_H__
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#include "base/bitunion.hh"
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#include "cpu/intr_control.hh"
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#include "dev/arm/base_gic.hh"
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#include "dev/io_device.hh"
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#include "dev/platform.hh"
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#include "params/Pl390.hh"
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/** @todo this code only assumes one processor for now. Low word
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* of intEnabled and pendingInt need to be replicated per CPU.
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* bottom 31 interrupts (7 words) need to be replicated for
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* for interrupt priority register, processor target registers
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* interrupt config registers */
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class Pl390 : public BaseGic
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{
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protected:
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// distributor memory addresses
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static const int ICDDCR = 0x000; // control register
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static const int ICDICTR = 0x004; // controller type
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static const int ICDIIDR = 0x008; // implementer id
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static const int ICDISER_ST = 0x100; // interrupt set enable
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static const int ICDISER_ED = 0x17c;
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static const int ICDICER_ST = 0x180; // interrupt clear enable
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static const int ICDICER_ED = 0x1fc;
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static const int ICDISPR_ST = 0x200; // set pending interrupt
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static const int ICDISPR_ED = 0x27c;
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static const int ICDICPR_ST = 0x280; // clear pending interrupt
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static const int ICDICPR_ED = 0x2fc;
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static const int ICDABR_ST = 0x300; // active bit registers
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static const int ICDABR_ED = 0x37c;
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static const int ICDIPR_ST = 0x400; // interrupt priority registers
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static const int ICDIPR_ED = 0x7f8;
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static const int ICDIPTR_ST = 0x800; // processor target registers
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static const int ICDIPTR_ED = 0xbf8;
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static const int ICDICFR_ST = 0xc00; // interrupt config registers
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static const int ICDICFR_ED = 0xcfc;
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static const int ICDSGIR = 0xf00; // software generated interrupt
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static const int DIST_SIZE = 0xfff;
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// cpu memory addressesa
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static const int ICCICR = 0x00; // CPU control register
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static const int ICCPMR = 0x04; // Interrupt priority mask
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static const int ICCBPR = 0x08; // binary point register
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static const int ICCIAR = 0x0C; // interrupt ack register
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static const int ICCEOIR = 0x10; // end of interrupt
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static const int ICCRPR = 0x14; // runing priority
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static const int ICCHPIR = 0x18; // highest pending interrupt
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static const int ICCABPR = 0x1c; // aliased binary point
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static const int ICCIIDR = 0xfc; // cpu interface id register
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static const int CPU_SIZE = 0xff;
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static const int SGI_MAX = 16; // Number of Software Gen Interrupts
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static const int PPI_MAX = 16; // Number of Private Peripheral Interrupts
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/** Mask off SGI's when setting/clearing pending bits */
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static const int SGI_MASK = 0xFFFF0000;
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/** Mask for bits that config N:N mode in ICDICFR's */
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static const int NN_CONFIG_MASK = 0x55555555;
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static const int CPU_MAX = 256; // Max number of supported CPU interfaces
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static const int SPURIOUS_INT = 1023;
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static const int INT_BITS_MAX = 32;
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static const int INT_LINES_MAX = 1020;
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BitUnion32(SWI)
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Bitfield<3,0> sgi_id;
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Bitfield<23,16> cpu_list;
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Bitfield<25,24> list_type;
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EndBitUnion(SWI)
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BitUnion32(IAR)
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Bitfield<9,0> ack_id;
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Bitfield<12,10> cpu_id;
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EndBitUnion(IAR)
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/** Distributor address GIC listens at */
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Addr distAddr;
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/** CPU address GIC listens at */
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/** @todo is this one per cpu? */
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Addr cpuAddr;
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/** Latency for a distributor operation */
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Tick distPioDelay;
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/** Latency for a cpu operation */
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Tick cpuPioDelay;
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/** Latency for a interrupt to get to CPU */
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Tick intLatency;
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/** Gic enabled */
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bool enabled;
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/** gem5 many-core extension enabled by driver */
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bool gem5ExtensionsEnabled;
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/** Number of itLines enabled */
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uint32_t itLines;
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uint32_t itLinesLog2;
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/** interrupt enable bits for all possible 1020 interupts.
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t intEnabled[INT_BITS_MAX];
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/** interrupt pending bits for all possible 1020 interupts.
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t pendingInt[INT_BITS_MAX];
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/** interrupt active bits for all possible 1020 interupts.
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* one bit per interrupt, 32 bit per word = 32 words */
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uint32_t activeInt[INT_BITS_MAX];
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/** read only running priroity register, 1 per cpu*/
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uint32_t iccrpr[CPU_MAX];
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/** an 8 bit priority (lower is higher priority) for each
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* of the 1020 possible supported interrupts.
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*/
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uint8_t intPriority[INT_LINES_MAX];
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/** an 8 bit cpu target id for each shared peripheral interrupt
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* of the 1020 possible supported interrupts.
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*/
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uint8_t cpuTarget[INT_LINES_MAX];
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/** 2 bit per interrupt signaling if it's level or edge sensitive
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* and if it is 1:N or N:N */
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uint32_t intConfig[INT_BITS_MAX*2];
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/** CPU enabled */
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bool cpuEnabled[CPU_MAX];
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/** CPU priority */
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uint8_t cpuPriority[CPU_MAX];
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/** Binary point registers */
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uint8_t cpuBpr[CPU_MAX];
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/** highest interrupt that is interrupting CPU */
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uint32_t cpuHighestInt[CPU_MAX];
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/** One bit per cpu per software interrupt that is pending for each possible
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* sgi source. Indexed by SGI number. Each byte in generating cpu id and
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* bits in position is destination id. e.g. 0x4 = CPU 0 generated interrupt
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* for CPU 2. */
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uint64_t cpuSgiPending[SGI_MAX];
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uint64_t cpuSgiActive[SGI_MAX];
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/** SGI pending arrays for gem5 GIC extension mode, which instead keeps
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* 16 SGI pending bits for each of the (large number of) CPUs.
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*/
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uint32_t cpuSgiPendingExt[CPU_MAX];
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uint32_t cpuSgiActiveExt[CPU_MAX];
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/** One bit per private peripheral interrupt. Only upper 16 bits
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* will be used since PPI interrupts are numberred from 16 to 32 */
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uint32_t cpuPpiPending[CPU_MAX];
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uint32_t cpuPpiActive[CPU_MAX];
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/** Banked interrupt prioirty registers for SGIs and PPIs */
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uint8_t bankedIntPriority[CPU_MAX][SGI_MAX + PPI_MAX];
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/** IRQ Enable Used for debug */
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bool irqEnable;
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/** software generated interrupt
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* @param data data to decode that indicates which cpus to interrupt
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*/
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void softInt(ContextID ctx_id, SWI swi);
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/** See if some processor interrupt flags need to be enabled/disabled
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* @param hint which set of interrupts needs to be checked
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*/
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void updateIntState(int hint);
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/** Update the register that records priority of the highest priority
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* active interrupt*/
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void updateRunPri();
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/** generate a bit mask to check cpuSgi for an interrupt. */
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uint64_t genSwiMask(int cpu);
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int intNumToWord(int num) const { return num >> 5; }
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int intNumToBit(int num) const { return num % 32; }
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/** Post an interrupt to a CPU
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*/
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void postInt(uint32_t cpu, Tick when);
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/** Event definition to post interrupt to CPU after a delay
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*/
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class PostIntEvent : public Event
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{
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private:
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uint32_t cpu;
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Platform *platform;
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public:
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PostIntEvent( uint32_t c, Platform* p)
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: cpu(c), platform(p)
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{ }
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void process() { platform->intrctrl->post(cpu, ArmISA::INT_IRQ, 0);}
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const char *description() const { return "Post Interrupt to CPU"; }
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};
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PostIntEvent *postIntEvent[CPU_MAX];
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public:
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typedef Pl390Params Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Pl390(const Params *p);
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/** @{ */
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/** Return the address ranges used by the Gic
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* This is the distributor address + all cpu addresses
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*/
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AddrRangeList getAddrRanges() const override;
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/** A PIO read to the device, immediately split up into
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* readDistributor() or readCpu()
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*/
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Tick read(PacketPtr pkt) override;
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/** A PIO read to the device, immediately split up into
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* writeDistributor() or writeCpu()
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*/
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Tick write(PacketPtr pkt) override;
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/** @} */
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/** @{ */
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/** Post an interrupt from a device that is connected to the Gic.
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* Depending on the configuration, the gic will pass this interrupt
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* on through to a CPU.
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* @param number number of interrupt to send */
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void sendInt(uint32_t number) override;
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/** Interface call for private peripheral interrupts */
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void sendPPInt(uint32_t num, uint32_t cpu) override;
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/** Clear an interrupt from a device that is connected to the Gic
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* Depending on the configuration, the gic may de-assert it's cpu line
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* @param number number of interrupt to send */
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void clearInt(uint32_t number) override;
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/** Clear a (level-sensitive) PPI */
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void clearPPInt(uint32_t num, uint32_t cpu) override;
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/** @} */
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/** @{ */
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/* Various functions fer testing and debugging */
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void driveSPI(uint32_t spi);
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void driveLegIRQ(bool state);
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void driveLegFIQ(bool state);
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void driveIrqEn(bool state);
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/** @} */
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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protected:
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/** Handle a read to the distributor poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick readDistributor(PacketPtr pkt);
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/** Handle a read to the cpu poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick readCpu(PacketPtr pkt);
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/** Handle a write to the distributor poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick writeDistributor(PacketPtr pkt);
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/** Handle a write to the cpu poriton of the GIC
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* @param pkt packet to respond to
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*/
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Tick writeCpu(PacketPtr pkt);
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};
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#endif //__DEV_ARM_GIC_H__
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