55f5c4dd8a
The current TLM bridge only provides a Slave Port that allows the gem5 world to send request to the SystemC world. This patch series refractors and cleans up the existing code, and adds a Master Port that allows the SystemC world to send requests to the gem5 world. This patch: * Add the Master Port. Add an example application that isslustrates its * use. Testing Done: A simple example application consisting of a TLM traffic generator and a gem5 memory is part of the patch. Reviewed at http://reviews.gem5.org/r/3528/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
154 lines
5.3 KiB
C++
154 lines
5.3 KiB
C++
/*
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Christian Menard
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*/
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#include "base/random.hh"
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#include "traffic_generator.hh"
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TrafficGenerator::TrafficGenerator(sc_core::sc_module_name name)
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: sc_core::sc_module(name),
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requestInProgress(0),
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peq(this, &TrafficGenerator::peq_cb)
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{
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socket.register_nb_transport_bw(this, &TrafficGenerator::nb_transport_bw);
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SC_THREAD(process);
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}
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void
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TrafficGenerator::process()
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{
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auto rnd = Random(time(NULL));
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unsigned const memSize = (1 << 10); // 512 MB
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while (true) {
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wait(sc_core::sc_time((double)rnd.random(1,100), sc_core::SC_NS));
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auto trans = mm.allocate();
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trans->acquire();
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std::string cmdStr;
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if (rnd.random(0,1)) // Generate a write request?
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{
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cmdStr = "write";
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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dataBuffer = rnd.random(0,0xffff);
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} else {
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cmdStr = "read";
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trans->set_command(tlm::TLM_READ_COMMAND);
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}
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trans->set_data_ptr(reinterpret_cast<unsigned char*>(&dataBuffer));
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trans->set_address(rnd.random(0, (int)(memSize-1)));
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trans->set_data_length(4);
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trans->set_streaming_width(4);
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trans->set_byte_enable_ptr(0);
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trans->set_dmi_allowed(0);
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trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
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// honor the BEGIN_REQ/END_REQ exclusion rule
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if (requestInProgress)
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sc_core::wait(endRequestEvent);
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std::stringstream ss;
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ss << "Send " << cmdStr << " request @0x" << std::hex
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<< trans->get_address();
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SC_REPORT_INFO("Traffic Generator", ss.str().c_str());
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// send the request
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requestInProgress = trans;
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tlm::tlm_phase phase = tlm::BEGIN_REQ;
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auto delay = sc_core::SC_ZERO_TIME;
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auto status = socket->nb_transport_fw(*trans, phase, delay);
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// Check status
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if (status == tlm::TLM_UPDATED) {
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peq.notify(*trans, phase, delay);
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} else if (status == tlm::TLM_COMPLETED) {
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requestInProgress = 0;
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checkTransaction(*trans);
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SC_REPORT_INFO("Traffic Generator", "request completed");
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trans->release();
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}
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}
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}
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void
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TrafficGenerator::peq_cb(tlm::tlm_generic_payload& trans,
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const tlm::tlm_phase& phase)
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{
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if (phase == tlm::END_REQ ||
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(&trans == requestInProgress && phase == tlm::BEGIN_RESP)) {
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// The end of the BEGIN_REQ phase
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requestInProgress = 0;
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endRequestEvent.notify();
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} else if (phase == tlm::BEGIN_REQ || phase == tlm::END_RESP)
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SC_REPORT_FATAL("TLM-2",
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"Illegal transaction phase received by initiator");
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if (phase == tlm::BEGIN_RESP) {
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checkTransaction(trans);
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SC_REPORT_INFO("Traffic Generator", "received response");
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// Send end response
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tlm::tlm_phase fw_phase = tlm::END_RESP;
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// stress the retry mechanism by deferring the response
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auto delay = sc_core::sc_time(5.0, sc_core::SC_NS);
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socket->nb_transport_fw(trans, fw_phase, delay);
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trans.release();
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}
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}
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void
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TrafficGenerator::checkTransaction(tlm::tlm_generic_payload& trans)
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{
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if (trans.is_response_error()) {
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std::stringstream ss;
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ss << "Transaction returned with error, response status = %s"
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<< trans.get_response_string();
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SC_REPORT_ERROR("TLM-2", ss.str().c_str());
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}
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}
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tlm::tlm_sync_enum
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TrafficGenerator::nb_transport_bw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase,
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sc_core::sc_time& delay)
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{
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trans.acquire();
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peq.notify(trans, phase, delay);
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return tlm::TLM_ACCEPTED;
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}
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