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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Andreas Hansson 8fe556338d stats: Update stats to reflect use of SimpleDRAM 
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
2012-10-25 13:14:42 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.898954 # Number of seconds simulated
sim_ticks 1898954186500 # Number of ticks simulated
final_tick 1898954186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 93254 # Simulator instruction rate (inst/s)
host_op_rate 93254 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3072830921 # Simulator tick rate (ticks/s)
host_mem_usage 330780 # Number of bytes of host memory used
host_seconds 617.98 # Real time elapsed on the host
sim_insts 57629320 # Number of instructions simulated
sim_ops 57629320 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 946048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24721152 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 36608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 493888 # Number of bytes read from this memory
system.physmem.bytes_read::total 28848320 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 946048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 36608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 982656 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7831936 # Number of bytes written to this memory
system.physmem.bytes_written::total 7831936 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 14782 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 386268 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 572 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 7717 # Number of read requests responded to by this memory
system.physmem.num_reads::total 450755 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 122374 # Number of write requests responded to by this memory
system.physmem.num_writes::total 122374 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 498194 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 13018298 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1395834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 19278 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 260084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 15191688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 498194 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 19278 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 517472 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4124342 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4124342 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4124342 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 498194 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 13018298 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1395834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 19278 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 260084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 19316030 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 450755 # Total number of read requests seen
system.physmem.writeReqs 122374 # Total number of write requests seen
system.physmem.cpureqs 604625 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28848320 # Total number of bytes read from memory
system.physmem.bytesWritten 7831936 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28848320 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7831936 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 7306 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28435 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28036 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28258 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 28415 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 28091 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 28033 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 28162 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 28315 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 27858 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 28248 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 28366 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 28107 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 28166 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 28158 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 28038 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 7848 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 7611 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 7694 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 7488 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 7537 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 7442 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 7588 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 7788 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 7389 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 7747 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 7895 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 7671 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7728 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 7650 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7483 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 772 # Number of times wr buffer was full causing retry
system.physmem.totGap 1898947634000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 450755 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 123146 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 7306 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 322964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66672 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 31035 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 6570 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2878 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2432 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1794 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1691 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1963 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1555 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1804 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1273 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1481 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 919 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 238 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 4068 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 5145 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 5193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 5273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 5291 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 5313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 5313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5313 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 5321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 5321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1253 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 6521684939 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 13830350939 # Sum of mem lat for all requests
system.physmem.totBusLat 1802760000 # Total cycles spent in databus access
system.physmem.totBankLat 5505906000 # Total cycles spent in bank access
system.physmem.avgQLat 14470.45 # Average queueing delay per request
system.physmem.avgBankLat 12216.61 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 30687.06 # Average memory access latency
system.physmem.avgRdBW 15.19 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.19 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 4.12 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 13.13 # Average write queue length over time
system.physmem.readRowHits 430277 # Number of row buffer hits during reads
system.physmem.writeRowHits 78021 # Number of row buffer hits during writes
system.physmem.readRowHitRate 95.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes
system.physmem.avgGap 3313298.81 # Average gap between requests
system.l2c.replacements 343856 # number of replacements
system.l2c.tagsinuse 65278.684390 # Cycle average of tags in use
system.l2c.total_refs 2547974 # Total number of references to valid blocks.
system.l2c.sampled_refs 408869 # Sample count of references to valid blocks.
system.l2c.avg_refs 6.231761 # Average number of references to valid blocks.
system.l2c.warmup_cycle 5415654002 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 53716.705985 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 5434.737424 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 5906.149934 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 139.277407 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 81.813640 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.819652 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.082928 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.090121 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.002125 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.001248 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996074 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 735942 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 661355 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 365668 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 116985 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1879950 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 792215 # number of Writeback hits
system.l2c.Writeback_hits::total 792215 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 181 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 554 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 735 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 48 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 77 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 120772 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 49783 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 170555 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 735942 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 782127 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 365668 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 166768 # number of demand (read+write) hits
system.l2c.demand_hits::total 2050505 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 735942 # number of overall hits
system.l2c.overall_hits::cpu0.data 782127 # number of overall hits
system.l2c.overall_hits::cpu1.inst 365668 # number of overall hits
system.l2c.overall_hits::cpu1.data 166768 # number of overall hits
system.l2c.overall_hits::total 2050505 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 14784 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 273448 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 589 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 372 # number of ReadReq misses
system.l2c.ReadReq_misses::total 289193 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 2956 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1861 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4817 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 961 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 970 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 113696 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 7374 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 121070 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 14784 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 387144 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 589 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 7746 # number of demand (read+write) misses
system.l2c.demand_misses::total 410263 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 14784 # number of overall misses
system.l2c.overall_misses::cpu0.data 387144 # number of overall misses
system.l2c.overall_misses::cpu1.inst 589 # number of overall misses
system.l2c.overall_misses::cpu1.data 7746 # number of overall misses
system.l2c.overall_misses::total 410263 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 905760500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 11767860000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 39830500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 25154000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 12738605000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 1223500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 10690992 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 11914492 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 822500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 139000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 961500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8153056000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 935278000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9088334000 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 905760500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 19920916000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 39830500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 960432000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 21826939000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 905760500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 19920916000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 39830500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 960432000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 21826939000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 750726 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 934803 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 366257 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 117357 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2169143 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 792215 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 792215 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3137 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2415 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5552 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 1009 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 999 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2008 # number of SCUpgradeReq accesses(hits+misses)
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system.iocache.overall_avg_miss_latency::total 228202.842448 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 192112 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 23026 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 8.343264 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11993000 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7338178524 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7338178524 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 7350171524 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7350171524 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 7350171524 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7350171524 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68925.287356 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68925.287356 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176602.294089 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 176602.294089 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176153.274313 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 176153.274313 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176153.274313 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 176153.274313 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 8153093 # DTB read hits
system.cpu0.dtb.read_misses 30801 # DTB read misses
system.cpu0.dtb.read_acv 546 # DTB read access violations
system.cpu0.dtb.read_accesses 631302 # DTB read accesses
system.cpu0.dtb.write_hits 5186191 # DTB write hits
system.cpu0.dtb.write_misses 6023 # DTB write misses
system.cpu0.dtb.write_acv 347 # DTB write access violations
system.cpu0.dtb.write_accesses 217125 # DTB write accesses
system.cpu0.dtb.data_hits 13339284 # DTB hits
system.cpu0.dtb.data_misses 36824 # DTB misses
system.cpu0.dtb.data_acv 893 # DTB access violations
system.cpu0.dtb.data_accesses 848427 # DTB accesses
system.cpu0.itb.fetch_hits 954719 # ITB hits
system.cpu0.itb.fetch_misses 30502 # ITB misses
system.cpu0.itb.fetch_acv 1031 # ITB acv
system.cpu0.itb.fetch_accesses 985221 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 96359628 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.BPredUnit.lookups 11511160 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 9658650 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 337362 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 8089137 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 5013359 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.usedRAS 738841 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 28813 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 22209501 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 59836413 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 11511160 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 5752200 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 11350991 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1703319 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 34574956 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 35024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 203611 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 316697 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 7365602 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 218420 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 69794661 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.857321 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.189603 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 58443670 83.74% 83.74% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 721745 1.03% 84.77% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1525948 2.19% 86.96% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 670208 0.96% 87.92% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 2529232 3.62% 91.54% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 511055 0.73% 92.27% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 558087 0.80% 93.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 646305 0.93% 94.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 4188411 6.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 69794661 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.119460 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.620970 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 23572170 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 33977525 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 10309860 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 863665 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1071440 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 494315 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 32656 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 58557743 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 90732 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1071440 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 24508121 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 14373596 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 16410684 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9644673 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 3786145 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 55387876 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 6888 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 592503 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1353497 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 37339158 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 67830341 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 67526671 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 303670 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 32375017 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4964141 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1283235 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 190076 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 10267361 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 8584787 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5466291 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1084962 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 724878 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 49128818 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1589448 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 47805943 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 98656 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 5900406 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 3193389 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1078704 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 69794661 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.684951 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.331704 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 48560473 69.58% 69.58% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9626391 13.79% 83.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 4360326 6.25% 89.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2905573 4.16% 93.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2277062 3.26% 97.04% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1128487 1.62% 98.66% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 610541 0.87% 99.53% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 278212 0.40% 99.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 47596 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 69794661 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 83272 13.43% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 13.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 288642 46.54% 59.97% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 248279 40.03% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3328 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 33277792 69.61% 69.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 52563 0.11% 69.73% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.73% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 13047 0.03% 69.75% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.75% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.75% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.75% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.76% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 8484999 17.75% 87.51% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5253957 10.99% 98.50% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 718601 1.50% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 47805943 # Type of FU issued
system.cpu0.iq.rate 0.496120 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 620193 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.012973 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 165689680 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 56419476 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 46799675 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 435716 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 211307 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 205983 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 48194794 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 228014 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 514272 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1137404 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2618 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 12330 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 467046 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 18608 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 143062 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1071440 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 10277613 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 727728 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 53688552 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 610167 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 8584787 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5466291 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1400307 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 521112 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 4713 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 12330 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 181936 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 316829 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 498765 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 47397397 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 8205181 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 408546 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 2970286 # number of nop insts executed
system.cpu0.iew.exec_refs 13410008 # number of memory reference insts executed
system.cpu0.iew.exec_branches 7582856 # Number of branches executed
system.cpu0.iew.exec_stores 5204827 # Number of stores executed
system.cpu0.iew.exec_rate 0.491880 # Inst execution rate
system.cpu0.iew.wb_sent 47094366 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 47005658 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 23624719 # num instructions producing a value
system.cpu0.iew.wb_consumers 31676204 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.487815 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.745819 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 6363159 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 510744 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 465851 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 68723221 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.687218 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.593416 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 50805017 73.93% 73.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7482510 10.89% 84.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 4158339 6.05% 90.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2211388 3.22% 94.08% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1226271 1.78% 95.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 519535 0.76% 96.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 434174 0.63% 97.26% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 401210 0.58% 97.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1484777 2.16% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 68723221 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 47227841 # Number of instructions committed
system.cpu0.commit.committedOps 47227841 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 12446628 # Number of memory references committed
system.cpu0.commit.loads 7447383 # Number of loads committed
system.cpu0.commit.membars 170869 # Number of memory barriers committed
system.cpu0.commit.branches 7170885 # Number of branches committed
system.cpu0.commit.fp_insts 203520 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 43794871 # Number of committed integer instructions.
system.cpu0.commit.function_calls 589410 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1484777 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 120629648 # The number of ROB reads
system.cpu0.rob.rob_writes 108253472 # The number of ROB writes
system.cpu0.timesIdled 983557 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 26564967 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3700831730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 44545141 # Number of Instructions Simulated
system.cpu0.committedOps 44545141 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 44545141 # Number of Instructions Simulated
system.cpu0.cpi 2.163191 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.163191 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.462280 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.462280 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 62595782 # number of integer regfile reads
system.cpu0.int_regfile_writes 34216642 # number of integer regfile writes
system.cpu0.fp_regfile_reads 100415 # number of floating regfile reads
system.cpu0.fp_regfile_writes 101247 # number of floating regfile writes
system.cpu0.misc_regfile_reads 1454133 # number of misc regfile reads
system.cpu0.misc_regfile_writes 720721 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.icache.replacements 750148 # number of replacements
system.cpu0.icache.tagsinuse 510.325521 # Cycle average of tags in use
system.cpu0.icache.total_refs 6574672 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 750660 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.758522 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 20341529000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 510.325521 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.996730 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.996730 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 6574672 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 6574672 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 6574672 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 6574672 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 6574672 # number of overall hits
system.cpu0.icache.overall_hits::total 6574672 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 790930 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 790930 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 790930 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 790930 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 790930 # number of overall misses
system.cpu0.icache.overall_misses::total 790930 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11244615993 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11244615993 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 11244615993 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11244615993 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 11244615993 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11244615993 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 7365602 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 7365602 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 7365602 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 7365602 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 7365602 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 7365602 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.107382 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.107382 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.107382 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.107382 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.107382 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.107382 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14216.954715 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14216.954715 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14216.954715 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14216.954715 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14216.954715 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14216.954715 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 2954 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 148 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.959459 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 318 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40102 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 40102 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 40102 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 40102 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 40102 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 40102 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 750828 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 750828 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 750828 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 750828 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 750828 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 750828 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9260198495 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 9260198495 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9260198495 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 9260198495 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9260198495 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 9260198495 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.101937 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.101937 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.101937 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.101937 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.101937 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.101937 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12333.315347 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12333.315347 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12333.315347 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12333.315347 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12333.315347 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12333.315347 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1172092 # number of replacements
system.cpu0.dcache.tagsinuse 505.853040 # Cycle average of tags in use
system.cpu0.dcache.total_refs 9524802 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1172488 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 8.123582 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 21811000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 505.853040 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.987994 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.987994 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5943112 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5943112 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3262323 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3262323 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143230 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 143230 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 162594 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 162594 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9205435 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9205435 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9205435 # number of overall hits
system.cpu0.dcache.overall_hits::total 9205435 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 1417911 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1417911 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1553318 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1553318 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17723 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 17723 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5875 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5875 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2971229 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2971229 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2971229 # number of overall misses
system.cpu0.dcache.overall_misses::total 2971229 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31710477500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 31710477500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68102427025 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 68102427025 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 236251500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 236251500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44454500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 44454500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 99812904525 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 99812904525 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 99812904525 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 99812904525 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7361023 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7361023 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4815641 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4815641 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160953 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 160953 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168469 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 168469 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12176664 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12176664 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12176664 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12176664 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.192624 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.192624 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322557 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.322557 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110113 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110113 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.034873 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.034873 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244010 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.244010 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244010 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.244010 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22364.222790 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 22364.222790 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43843.196966 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43843.196966 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13330.220617 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13330.220617 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7566.723404 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7566.723404 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33593.137562 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33593.137562 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33593.137562 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33593.137562 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 2427231 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1005 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 46334 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 52.385527 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 143.571429 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 669951 # number of writebacks
system.cpu0.dcache.writebacks::total 669951 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 478870 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 478870 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1309589 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1309589 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3866 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3866 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1788459 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1788459 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1788459 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1788459 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939041 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 939041 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 243729 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 243729 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13857 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13857 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5874 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5874 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182770 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1182770 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182770 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1182770 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20515201000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20515201000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9973935364 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9973935364 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136652000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136652000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32706500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32706500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30489136364 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 30489136364 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30489136364 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 30489136364 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1471717500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1471717500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2287191498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2287191498 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3758908998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3758908998 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127569 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127569 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050612 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050612 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086093 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086093 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.034867 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.034867 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097134 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.097134 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097134 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.097134 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21846.970473 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21846.970473 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40922.234794 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40922.234794 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9861.586202 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9861.586202 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5568.011576 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5568.011576 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25777.739006 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25777.739006 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25777.739006 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25777.739006 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 2751784 # DTB read hits
system.cpu1.dtb.read_misses 11470 # DTB read misses
system.cpu1.dtb.read_acv 7 # DTB read access violations
system.cpu1.dtb.read_accesses 320817 # DTB read accesses
system.cpu1.dtb.write_hits 1920140 # DTB write hits
system.cpu1.dtb.write_misses 2953 # DTB write misses
system.cpu1.dtb.write_acv 42 # DTB write access violations
system.cpu1.dtb.write_accesses 122077 # DTB write accesses
system.cpu1.dtb.data_hits 4671924 # DTB hits
system.cpu1.dtb.data_misses 14423 # DTB misses
system.cpu1.dtb.data_acv 49 # DTB access violations
system.cpu1.dtb.data_accesses 442894 # DTB accesses
system.cpu1.itb.fetch_hits 498760 # ITB hits
system.cpu1.itb.fetch_misses 8025 # ITB misses
system.cpu1.itb.fetch_acv 112 # ITB acv
system.cpu1.itb.fetch_accesses 506785 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 23450533 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.BPredUnit.lookups 3776767 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 3137470 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 107427 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 2636449 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 1329693 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.usedRAS 256698 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 10696 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 9578000 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 17862357 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 3776767 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 1586391 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 3193569 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 532728 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 8846684 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 29714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 64849 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 64234 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.CacheLines 2092153 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 72512 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 22109536 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.807903 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.182028 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 18915967 85.56% 85.56% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 225371 1.02% 86.58% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 332195 1.50% 88.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 235368 1.06% 89.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 429129 1.94% 91.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 160604 0.73% 91.81% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 176264 0.80% 92.61% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 387732 1.75% 94.36% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 1246906 5.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 22109536 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.161053 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.761704 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 9287856 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 9344742 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 2981707 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 172176 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 323054 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 161936 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 9554 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 17577560 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 27080 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 323054 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 9598975 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 567037 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 7834145 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 2842462 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 943861 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 16294411 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 85147 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 230847 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 10570715 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 19279832 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 19004281 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 275551 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 9242282 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 1328425 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 653029 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 73319 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 2960053 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 2891333 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 2010374 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 258927 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 184993 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 14228135 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 747471 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 13980669 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 34327 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 1780795 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 830376 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 520995 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 22109536 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.632337 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.304677 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 15925897 72.03% 72.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 2876428 13.01% 85.04% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 1188641 5.38% 90.42% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 788361 3.57% 93.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 710967 3.22% 97.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 312206 1.41% 98.61% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 203719 0.92% 99.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 91872 0.42% 99.95% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 11445 0.05% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 22109536 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 4072 1.54% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.54% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 138321 52.40% 53.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 121563 46.05% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 3973 0.03% 0.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 8718475 62.36% 62.39% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 23525 0.17% 62.56% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 14518 0.10% 62.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.66% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1986 0.01% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.68% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 2887601 20.65% 83.33% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 1950660 13.95% 97.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 379931 2.72% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 13980669 # Type of FU issued
system.cpu1.iq.rate 0.596177 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 263956 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.018880 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 49973211 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 16565755 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 13576031 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 395945 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 192396 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 186883 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 14033908 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 206744 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 127652 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 343707 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 718 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 1847 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 149646 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 268 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 8933 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 323054 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 323914 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 83587 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 15804070 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 217247 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 2891333 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 2010374 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 666348 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 75335 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 2938 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 1847 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 54178 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 138289 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 192467 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 13856768 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 2775542 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 123900 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 828464 # number of nop insts executed
system.cpu1.iew.exec_refs 4708126 # number of memory reference insts executed
system.cpu1.iew.exec_branches 2079937 # Number of branches executed
system.cpu1.iew.exec_stores 1932584 # Number of stores executed
system.cpu1.iew.exec_rate 0.590894 # Inst execution rate
system.cpu1.iew.wb_sent 13794604 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 13762914 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 6356145 # num instructions producing a value
system.cpu1.iew.wb_consumers 9022133 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.586891 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.704506 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 1892811 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 226476 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 180279 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 21786482 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.634671 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.584399 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 16693912 76.63% 76.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 2323450 10.66% 87.29% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 881751 4.05% 91.34% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 546550 2.51% 93.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 424121 1.95% 95.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 149663 0.69% 96.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 143043 0.66% 97.14% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 194342 0.89% 98.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 429650 1.97% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 21786482 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 13827253 # Number of instructions committed
system.cpu1.commit.committedOps 13827253 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 4408354 # Number of memory references committed
system.cpu1.commit.loads 2547626 # Number of loads committed
system.cpu1.commit.membars 77059 # Number of memory barriers committed
system.cpu1.commit.branches 1974738 # Number of branches committed
system.cpu1.commit.fp_insts 185573 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 12741220 # Number of committed integer instructions.
system.cpu1.commit.function_calls 216858 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 429650 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 36982885 # The number of ROB reads
system.cpu1.rob.rob_writes 31761465 # The number of ROB writes
system.cpu1.timesIdled 211192 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 1340997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3774455201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 13084179 # Number of Instructions Simulated
system.cpu1.committedOps 13084179 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 13084179 # Number of Instructions Simulated
system.cpu1.cpi 1.792282 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.792282 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.557948 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.557948 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 17801475 # number of integer regfile reads
system.cpu1.int_regfile_writes 9673582 # number of integer regfile writes
system.cpu1.fp_regfile_reads 97896 # number of floating regfile reads
system.cpu1.fp_regfile_writes 98917 # number of floating regfile writes
system.cpu1.misc_regfile_reads 828029 # number of misc regfile reads
system.cpu1.misc_regfile_writes 335588 # number of misc regfile writes
system.cpu1.icache.replacements 365714 # number of replacements
system.cpu1.icache.tagsinuse 472.361820 # Cycle average of tags in use
system.cpu1.icache.total_refs 1714322 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 366225 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 4.681062 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1888132363000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 472.361820 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.922582 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.922582 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 1714323 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 1714323 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 1714323 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 1714323 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 1714323 # number of overall hits
system.cpu1.icache.overall_hits::total 1714323 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 377830 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 377830 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 377830 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 377830 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 377830 # number of overall misses
system.cpu1.icache.overall_misses::total 377830 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5021047500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5021047500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5021047500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5021047500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5021047500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5021047500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 2092153 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 2092153 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 2092153 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 2092153 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 2092153 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 2092153 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.180594 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.180594 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.180594 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.180594 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.180594 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.180594 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13289.171056 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13289.171056 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13289.171056 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13289.171056 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13289.171056 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13289.171056 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 20 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 3.333333 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11532 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 11532 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 11532 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 11532 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 11532 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 11532 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366298 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 366298 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 366298 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 366298 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366298 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 366298 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4196886000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4196886000 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4196886000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4196886000 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4196886000 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4196886000 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.175082 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.175082 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.175082 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.175082 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.175082 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.175082 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11457.572796 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11457.572796 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11457.572796 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11457.572796 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11457.572796 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11457.572796 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 177713 # number of replacements
system.cpu1.dcache.tagsinuse 493.227826 # Cycle average of tags in use
system.cpu1.dcache.total_refs 3781655 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 178225 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 21.218432 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 31174945000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 493.227826 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.963336 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.963336 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 2216837 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2216837 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1431438 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1431438 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 57301 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 57301 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56389 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 56389 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3648275 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3648275 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3648275 # number of overall hits
system.cpu1.dcache.overall_hits::total 3648275 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 345575 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 345575 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 359483 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 359483 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10381 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6326 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 6326 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 705058 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 705058 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 705058 # number of overall misses
system.cpu1.dcache.overall_misses::total 705058 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4984534000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 4984534000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10785650333 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 10785650333 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103272500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 103272500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 46472500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 46472500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 15770184333 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 15770184333 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 15770184333 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 15770184333 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2562412 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2562412 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1790921 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1790921 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67682 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 67682 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 62715 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 62715 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 4353333 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 4353333 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 4353333 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 4353333 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.134863 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.134863 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.200725 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.200725 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153379 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153379 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100869 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100869 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.161958 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.161958 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.161958 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.161958 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14423.884830 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14423.884830 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30003.227783 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 30003.227783 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9948.222715 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9948.222715 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.269365 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.269365 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22367.215652 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 22367.215652 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22367.215652 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 22367.215652 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 367146 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 4032 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 91.058036 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 122264 # number of writebacks
system.cpu1.dcache.writebacks::total 122264 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 218997 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 218997 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 293003 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 293003 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 737 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 737 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 512000 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 512000 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 512000 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 512000 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 126578 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 126578 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 66480 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 66480 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9644 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9644 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6325 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 6325 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 193058 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 193058 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 193058 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 193058 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1500682500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1500682500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1627145493 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1627145493 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75395000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75395000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33822500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33822500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3127827993 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 3127827993 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3127827993 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 3127827993 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718992500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718992500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737091000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737091000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049398 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049398 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037121 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037121 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.142490 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.142490 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100853 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100853 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044347 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.044347 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044347 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.044347 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11855.792476 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11855.792476 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24475.714395 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24475.714395 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7817.814185 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.814185 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5347.430830 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5347.430830 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16201.493815 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16201.493815 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6891 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 160705 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 55206 40.22% 40.22% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 141 0.10% 40.32% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1925 1.40% 41.72% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 459 0.33% 42.06% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 79532 57.94% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 137263 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 54744 49.07% 49.07% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 141 0.13% 49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1925 1.73% 50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 459 0.41% 51.34% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 54290 48.66% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 111559 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1864428350500 98.20% 98.20% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 66694000 0.00% 98.20% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 571257500 0.03% 98.23% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 222612500 0.01% 98.25% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 33310195000 1.75% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1898599109500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.991631 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.682618 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.812739 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 540 0.37% 0.37% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.37% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.37% # number of callpals executed
system.cpu0.kern.callpal::swpctx 2997 2.06% 2.43% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.04% 2.47% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.47% # number of callpals executed
system.cpu0.kern.callpal::swpipl 130488 89.67% 92.14% # number of callpals executed
system.cpu0.kern.callpal::rdps 6655 4.57% 96.71% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed
system.cpu0.kern.callpal::rti 4254 2.92% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 145528 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6813 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1282
system.cpu0.kern.mode_good::user 1282
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.188170 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.316739 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1896637292000 99.90% 99.90% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 1952797500 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 2998 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2640 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 82284 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 28208 38.75% 38.75% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1924 2.64% 41.39% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 540 0.74% 42.13% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 42124 57.87% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 72796 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 27293 48.30% 48.30% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1924 3.40% 51.70% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 540 0.96% 52.66% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 26753 47.34% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 56510 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1872083396500 98.59% 98.59% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 532362500 0.03% 98.61% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 246280000 0.01% 98.63% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 26091314000 1.37% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1898953353000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.967562 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.635101 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.776279 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 459 0.61% 0.61% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
system.cpu1.kern.callpal::swpctx 2146 2.85% 3.47% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.47% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.48% # number of callpals executed
system.cpu1.kern.callpal::swpipl 66489 88.37% 91.85% # number of callpals executed
system.cpu1.kern.callpal::rdps 2102 2.79% 94.64% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.64% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 94.65% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.65% # number of callpals executed
system.cpu1.kern.callpal::rti 3842 5.11% 99.76% # number of callpals executed
system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 75240 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2162 # number of protection mode switches
system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 928
system.cpu1.kern.mode_good::user 464
system.cpu1.kern.mode_good::idle 464
system.cpu1.kern.mode_switch_good::kernel 0.429232 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.158795 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.334535 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 8174267000 0.43% 0.43% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 802919500 0.04% 0.47% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1889976158500 99.53% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 2147 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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