gem5/tests/configs/tsunami-simple-timing.py
Andreas Hansson d22796c03c config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.
2012-10-25 04:32:44 -04:00

60 lines
2.5 KiB
Python

# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Steve Reinhardt
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
from Caches import *
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
#the system
system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
#create the iocache
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
cpu.connectAllPorts(system.membus)
# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('1THz')