gem5/src
Andreas Hansson 6f6adbf0f6 dev: Make default clock more reasonable for system and devices
This patch changes the default system clock from 1THz to 1GHz. This
clock is used by all modules that do not override the default (parent
clock), and primarily affects the IO subsystem. Every DMA device uses
its clock to schedule the next transfer, and the change will thus
cause this inter-transfer delay to be longer.

The default clock of the bus is removed, as the clock inherited from
the system provides exactly the same value.

A follow-on patch will bump the stats.
2012-10-25 13:14:44 -04:00
..
arch arm: Use table walker clock that is inherited from CPU 2012-10-25 04:32:42 -04:00
base Mem: Use range operations in bus in preparation for striping 2012-10-15 08:07:04 -04:00
cpu memtest: move check on outstanding requests 2012-10-15 17:27:17 -05:00
dev dev: Remove zero-time loop in DMA timing send 2012-10-23 04:49:33 -04:00
doc MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex 2012-09-21 04:51:18 -04:00
mem dev: Make default clock more reasonable for system and devices 2012-10-25 13:14:44 -04:00
python Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
sim dev: Make default clock more reasonable for system and devices 2012-10-25 13:14:44 -04:00
unittest AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript build: Add missing dependencies when building param SWIG interfaces 2012-09-25 11:49:40 -05:00