20e9a90edc
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
90 lines
2.2 KiB
C++
90 lines
2.2 KiB
C++
// -*- mode:c++ -*-
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Nop
|
|
//
|
|
|
|
output header {{
|
|
/**
|
|
* Static instruction class for no-ops. This is a leaf class.
|
|
*/
|
|
class Nop : public MipsStaticInst
|
|
{
|
|
/// Disassembly of original instruction.
|
|
const std::string originalDisassembly;
|
|
|
|
public:
|
|
/// Constructor
|
|
Nop(const std::string _originalDisassembly, MachInst _machInst)
|
|
: MipsStaticInst("nop", _machInst, No_OpClass),
|
|
originalDisassembly(_originalDisassembly)
|
|
{
|
|
flags[IsNop] = true;
|
|
}
|
|
|
|
~Nop() { }
|
|
|
|
std::string
|
|
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
|
|
|
|
%(BasicExecDeclare)s
|
|
};
|
|
}};
|
|
|
|
output decoder {{
|
|
std::string Nop::generateDisassembly(Addr pc,
|
|
const SymbolTable *symtab) const
|
|
{
|
|
#ifdef SS_COMPATIBLE_DISASSEMBLY
|
|
return originalDisassembly;
|
|
#else
|
|
return csprintf("%-10s (%s)", "nop", originalDisassembly);
|
|
#endif
|
|
}
|
|
|
|
/// Helper function for decoding nops. Substitute Nop object
|
|
/// for original inst passed in as arg (and delete latter).
|
|
inline
|
|
MipsStaticInst *
|
|
makeNop(MipsStaticInst *inst)
|
|
{
|
|
MipsStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
|
|
delete inst;
|
|
return nop;
|
|
}
|
|
}};
|
|
|
|
output exec {{
|
|
Fault
|
|
Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
|
|
{
|
|
return NoFault;
|
|
}
|
|
}};
|
|
|
|
// integer & FP operate instructions use RT as dest, so check for
|
|
// RT == 0 to detect nops
|
|
def template OperateNopCheckDecode {{
|
|
{
|
|
MipsStaticInst *i = new %(class_name)s(machInst);
|
|
|
|
//if (RD == 0) {
|
|
// i = makeNop(i);
|
|
//}
|
|
|
|
return i;
|
|
}
|
|
}};
|
|
|
|
|
|
// Like BasicOperate format, but generates NOP if RC/FC == 31
|
|
def format BasicOperateWithNopCheck(code, *opt_args) {{
|
|
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code),
|
|
opt_args)
|
|
header_output = BasicDeclare.subst(iop)
|
|
decoder_output = BasicConstructor.subst(iop)
|
|
decode_block = OperateNopCheckDecode.subst(iop)
|
|
exec_output = BasicExecute.subst(iop)
|
|
}};
|
|
|