6f4bd2c1da
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
458 lines
15 KiB
C++
458 lines
15 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#ifndef __CPU_O3_COMMIT_HH__
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#define __CPU_O3_COMMIT_HH__
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_seq.hh"
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class DerivO3CPUParams;
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template <class>
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class O3ThreadState;
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/**
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* DefaultCommit handles single threaded and SMT commit. Its width is
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* specified by the parameters; each cycle it tries to commit that
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* many instructions. The SMT policy decides which thread it tries to
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* commit instructions from. Non- speculative instructions must reach
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* the head of the ROB before they are ready to execute; once they
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* reach the head, commit will broadcast the instruction's sequence
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* number to the previous stages so that they can issue/ execute the
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* instruction. Only one non-speculative instruction is handled per
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* cycle. Commit is responsible for handling all back-end initiated
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* redirects. It receives the redirect, and then broadcasts it to all
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* stages, indicating the sequence number they should squash until,
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* and any necessary branch misprediction information as well. It
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* priortizes redirects by instruction's age, only broadcasting a
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* redirect if it corresponds to an instruction that should currently
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* be in the ROB. This is done by tracking the sequence number of the
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* youngest instruction in the ROB, which gets updated to any
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* squashing instruction's sequence number, and only broadcasting a
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* redirect if it corresponds to an older instruction. Commit also
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* supports multiple cycle squashing, to model a ROB that can only
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* remove a certain number of instructions per cycle.
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*/
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template<class Impl>
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class DefaultCommit
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{
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public:
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// Typedefs from the Impl.
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typedef typename Impl::O3CPU O3CPU;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::CPUPol CPUPol;
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typedef typename CPUPol::RenameMap RenameMap;
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typedef typename CPUPol::ROB ROB;
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typedef typename CPUPol::TimeStruct TimeStruct;
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::IEWStruct IEWStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::Fetch Fetch;
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typedef typename CPUPol::IEW IEW;
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typedef O3ThreadState<Impl> Thread;
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/** Event class used to schedule a squash due to a trap (fault or
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* interrupt) to happen on a specific cycle.
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*/
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class TrapEvent : public Event {
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private:
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DefaultCommit<Impl> *commit;
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ThreadID tid;
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public:
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TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
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void process();
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const char *description() const;
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};
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/** Overall commit status. Used to determine if the CPU can deschedule
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* itself due to a lack of activity.
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*/
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enum CommitStatus{
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Active,
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Inactive
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};
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/** Individual thread status. */
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enum ThreadStatus {
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Running,
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Idle,
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ROBSquashing,
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TrapPending,
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FetchTrapPending
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};
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/** Commit policy for SMT mode. */
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enum CommitPolicy {
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Aggressive,
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RoundRobin,
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OldestReady
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};
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private:
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/** Overall commit status. */
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CommitStatus _status;
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/** Next commit status, to be set at the end of the cycle. */
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CommitStatus _nextStatus;
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/** Per-thread status. */
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ThreadStatus commitStatus[Impl::MaxThreads];
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/** Commit policy used in SMT mode. */
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CommitPolicy commitPolicy;
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public:
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/** Construct a DefaultCommit with the given parameters. */
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DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
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/** Returns the name of the DefaultCommit. */
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std::string name() const;
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/** Registers statistics. */
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void regStats();
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/** Sets the list of threads. */
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void setThreads(std::vector<Thread *> &threads);
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/** Sets the main time buffer pointer, used for backwards communication. */
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
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/** Sets the pointer to the queue coming from rename. */
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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/** Sets the pointer to the queue coming from IEW. */
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void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
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/** Sets the pointer to the IEW stage. */
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void setIEWStage(IEW *iew_stage);
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/** Skid buffer between rename and commit. */
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std::queue<DynInstPtr> skidBuffer;
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/** The pointer to the IEW stage. Used solely to ensure that
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* various events (traps, interrupts, syscalls) do not occur until
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* all stores have written back.
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*/
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IEW *iewStage;
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/** Sets pointer to list of active threads. */
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void setActiveThreads(std::list<ThreadID> *at_ptr);
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/** Sets pointer to the commited state rename map. */
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void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
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/** Sets pointer to the ROB. */
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void setROB(ROB *rob_ptr);
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/** Initializes stage by sending back the number of free entries. */
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void initStage();
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/** Initializes the draining of commit. */
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bool drain();
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/** Resumes execution after draining. */
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void resume();
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/** Completes the switch out of commit. */
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void switchOut();
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/** Takes over from another CPU's thread. */
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void takeOverFrom();
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/** Ticks the commit stage, which tries to commit instructions. */
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void tick();
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/** Handles any squashes that are sent from IEW, and adds instructions
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* to the ROB and tries to commit instructions.
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*/
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void commit();
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/** Returns the number of free ROB entries for a specific thread. */
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size_t numROBFreeEntries(ThreadID tid);
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/** Generates an event to schedule a squash due to a trap. */
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void generateTrapEvent(ThreadID tid);
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/** Records that commit needs to initiate a squash due to an
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* external state update through the TC.
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*/
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void generateTCEvent(ThreadID tid);
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private:
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/** Updates the overall status of commit with the nextStatus, and
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* tell the CPU if commit is active/inactive.
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*/
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void updateStatus();
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/** Sets the next status based on threads' statuses, which becomes the
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* current status at the end of the cycle.
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*/
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void setNextStatus();
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/** Checks if the ROB is completed with squashing. This is for the case
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* where the ROB can take multiple cycles to complete squashing.
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*/
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bool robDoneSquashing();
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/** Returns if any of the threads have the number of ROB entries changed
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* on this cycle. Used to determine if the number of free ROB entries needs
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* to be sent back to previous stages.
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*/
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bool changedROBEntries();
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/** Squashes all in flight instructions. */
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void squashAll(ThreadID tid);
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/** Handles squashing due to a trap. */
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void squashFromTrap(ThreadID tid);
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/** Handles squashing due to an TC write. */
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void squashFromTC(ThreadID tid);
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#if FULL_SYSTEM
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/** Handles processing an interrupt. */
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void handleInterrupt();
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#endif // FULL_SYSTEM
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/** Commits as many instructions as possible. */
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void commitInsts();
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/** Tries to commit the head ROB instruction passed in.
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* @param head_inst The instruction to be committed.
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*/
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bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
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/** Gets instructions from rename and inserts them into the ROB. */
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void getInsts();
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/** Insert all instructions from rename into skidBuffer */
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void skidInsert();
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/** Marks completed instructions using information sent from IEW. */
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void markCompletedInsts();
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/** Gets the thread to commit, based on the SMT policy. */
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ThreadID getCommittingThread();
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/** Returns the thread ID to use based on a round robin policy. */
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ThreadID roundRobin();
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/** Returns the thread ID to use based on an oldest instruction policy. */
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ThreadID oldestReady();
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public:
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/** Reads the PC of a specific thread. */
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TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
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/** Sets the PC of a specific thread. */
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void pcState(const TheISA::PCState &val, ThreadID tid)
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{ pc[tid] = val; }
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/** Returns the PC of a specific thread. */
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Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
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/** Returns the next PC of a specific thread. */
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Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
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/** Reads the micro PC of a specific thread. */
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Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
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private:
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to write information heading to previous stages. */
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typename TimeBuffer<TimeStruct>::wire toIEW;
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/** Wire to read information from IEW (for ROB). */
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typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
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TimeBuffer<FetchStruct> *fetchQueue;
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typename TimeBuffer<FetchStruct>::wire fromFetch;
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/** IEW instruction queue interface. */
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TimeBuffer<IEWStruct> *iewQueue;
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/** Wire to read information from IEW queue. */
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typename TimeBuffer<IEWStruct>::wire fromIEW;
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/** Rename instruction queue interface, for ROB. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to read information from rename queue. */
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typename TimeBuffer<RenameStruct>::wire fromRename;
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public:
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/** ROB interface. */
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ROB *rob;
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private:
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/** Pointer to O3CPU. */
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O3CPU *cpu;
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/** Vector of all of the threads. */
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std::vector<Thread *> thread;
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/** Records that commit has written to the time buffer this cycle. Used for
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* the CPU to determine if it can deschedule itself if there is no activity.
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*/
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bool wroteToTimeBuffer;
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/** Records if the number of ROB entries has changed this cycle. If it has,
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* then the number of free entries must be re-broadcast.
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*/
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bool changedROBNumEntries[Impl::MaxThreads];
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/** A counter of how many threads are currently squashing. */
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ThreadID squashCounter;
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/** Records if a thread has to squash this cycle due to a trap. */
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bool trapSquash[Impl::MaxThreads];
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/** Records if a thread has to squash this cycle due to an XC write. */
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bool tcSquash[Impl::MaxThreads];
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/** Priority List used for Commit Policy */
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std::list<ThreadID> priority_list;
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/** IEW to Commit delay, in ticks. */
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unsigned iewToCommitDelay;
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/** Commit to IEW delay, in ticks. */
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unsigned commitToIEWDelay;
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/** Rename to ROB delay, in ticks. */
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unsigned renameToROBDelay;
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unsigned fetchToCommitDelay;
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/** Rename width, in instructions. Used so ROB knows how many
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* instructions to get from the rename instruction queue.
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*/
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unsigned renameWidth;
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/** Commit width, in instructions. */
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unsigned commitWidth;
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/** Number of Reorder Buffers */
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unsigned numRobs;
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/** Number of Active Threads */
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ThreadID numThreads;
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/** Is a drain pending. */
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bool drainPending;
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/** Is commit switched out. */
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bool switchedOut;
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/** The latency to handle a trap. Used when scheduling trap
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* squash event.
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*/
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Tick trapLatency;
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/** The interrupt fault. */
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Fault interrupt;
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/** The commit PC state of each thread. Refers to the instruction that
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* is currently being processed/committed.
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*/
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TheISA::PCState pc[Impl::MaxThreads];
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/** The sequence number of the youngest valid instruction in the ROB. */
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InstSeqNum youngestSeqNum[Impl::MaxThreads];
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/** Records if there is a trap currently in flight. */
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bool trapInFlight[Impl::MaxThreads];
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/** Records if there were any stores committed this cycle. */
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bool committedStores[Impl::MaxThreads];
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/** Records if commit should check if the ROB is truly empty (see
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commit_impl.hh). */
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bool checkEmptyROB[Impl::MaxThreads];
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/** Pointer to the list of active threads. */
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std::list<ThreadID> *activeThreads;
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/** Rename map interface. */
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RenameMap *renameMap[Impl::MaxThreads];
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/** Updates commit stats based on this instruction. */
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void updateComInstStats(DynInstPtr &inst);
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/** Stat for the total number of committed instructions. */
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Stats::Scalar commitCommittedInsts;
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/** Stat for the total number of squashed instructions discarded by commit.
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*/
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Stats::Scalar commitSquashedInsts;
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/** Stat for the total number of times commit is told to squash.
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* @todo: Actually increment this stat.
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*/
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Stats::Scalar commitSquashEvents;
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/** Stat for the total number of times commit has had to stall due to a non-
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* speculative instruction reaching the head of the ROB.
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*/
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Stats::Scalar commitNonSpecStalls;
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/** Stat for the total number of branch mispredicts that caused a squash. */
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Stats::Scalar branchMispredicts;
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/** Distribution of the number of committed instructions each cycle. */
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Stats::Distribution numCommittedDist;
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/** Total number of instructions committed. */
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Stats::Vector statComInst;
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/** Total number of software prefetches committed. */
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Stats::Vector statComSwp;
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/** Stat for the total number of committed memory references. */
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Stats::Vector statComRefs;
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/** Stat for the total number of committed loads. */
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Stats::Vector statComLoads;
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/** Total number of committed memory barriers. */
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Stats::Vector statComMembars;
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/** Total number of committed branches. */
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Stats::Vector statComBranches;
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/** Number of cycles where the commit bandwidth limit is reached. */
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Stats::Scalar commitEligibleSamples;
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/** Number of instructions not committed due to bandwidth limits. */
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Stats::Vector commitEligible;
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};
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#endif // __CPU_O3_COMMIT_HH__
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