205 lines
23 KiB
Text
205 lines
23 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 183914 # Simulator instruction rate (inst/s)
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host_mem_usage 203340 # Number of bytes of host memory used
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host_seconds 0.05 # Real time elapsed on the host
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host_tick_rate 573138759 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 9494 # Number of instructions simulated
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sim_seconds 0.000030 # Number of seconds simulated
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sim_ticks 29731000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 999 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3024000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.051282 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 2862000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.051282 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1835 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 8512000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.076497 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 152 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 8056000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.076497 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1835 # number of overall hits
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system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 152 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 8056000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.076497 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 80.872189 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_accesses 6887 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 6659 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.033106 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.033106 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 29.206140 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 6887 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
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system.cpu.icache.demand_hits 6659 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.033106 # miss rate for demand accesses
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system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.033106 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 6887 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 6659 # number of overall hits
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system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.033106 # miss rate for overall accesses
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system.cpu.icache.overall_misses 228 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.033106 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 106.638328 # Cycle average of tags in use
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system.cpu.icache.total_refs 6659 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 282 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 14612000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.996454 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 281 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 11240000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996454 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 281 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 18720000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.997230 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 360 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 14400000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.997230 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 360 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 360 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 14400000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.997230 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 360 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 128.120518 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 59462 # number of cpu cycles simulated
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system.cpu.num_insts 9494 # Number of instructions executed
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system.cpu.num_refs 1987 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
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---------- End Simulation Statistics ----------
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