417 lines
14 KiB
Text
417 lines
14 KiB
Text
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================ Begin RubySystem Configuration Print ================
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RubySystem config:
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random_seed: 184716
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randomization: 0
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tech_nm: 45
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freq_mhz: 3000
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block_size_bytes: 64
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block_size_bits: 6
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memory_size_bytes: 1073741824
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memory_size_bits: 30
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DMA_Controller config: DMAController_0
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version: 0
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buffer_size: 32
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dma_sequencer: DMASequencer_0
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number_of_TBEs: 128
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transitions_per_cycle: 32
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Directory_Controller config: DirectoryController_0
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version: 0
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buffer_size: 32
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directory_latency: 6
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directory_name: DirectoryMemory_0
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memory_controller_name: MemoryControl_0
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memory_latency: 158
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number_of_TBEs: 128
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recycle_latency: 10
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to_mem_ctrl_latency: 1
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transitions_per_cycle: 32
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L1Cache_Controller config: L1CacheController_0
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version: 0
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buffer_size: 32
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cache: l1u_0
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cache_response_latency: 12
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issue_latency: 2
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number_of_TBEs: 128
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sequencer: Sequencer_0
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transitions_per_cycle: 32
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Cache config: l1u_0
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controller: L1CacheController_0
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cache_associativity: 8
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num_cache_sets_bits: 2
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num_cache_sets: 4
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cache_set_size_bytes: 256
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cache_set_size_Kbytes: 0.25
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cache_set_size_Mbytes: 0.000244141
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cache_size_bytes: 2048
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cache_size_Kbytes: 2
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cache_size_Mbytes: 0.00195312
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DirectoryMemory Global Config:
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number of directory memories: 1
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total memory size bytes: 1073741824
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total memory size bits: 30
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DirectoryMemory module config: DirectoryMemory_0
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controller: DirectoryController_0
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version: 0
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memory_bits: 30
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memory_size_bytes: 1073741824
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memory_size_Kbytes: 1.04858e+06
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memory_size_Mbytes: 1024
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memory_size_Gbytes: 1
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Seqeuncer config: Sequencer_0
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controller: L1CacheController_0
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version: 0
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max_outstanding_requests: 16
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deadlock_threshold: 500000
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology: theTopology
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virtual_net_0: active, ordered
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virtual_net_1: active, ordered
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virtual_net_2: active, ordered
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virtual_net_3: inactive
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virtual_net_4: active, ordered
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virtual_net_5: active, ordered
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--- Begin Topology Print ---
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Topology print ONLY indicates the _NETWORK_ latency between two machines
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It does NOT include the latency within the machines
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L1Cache-0 Network Latencies
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L1Cache-0 -> Directory-0 net_lat: 7
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L1Cache-0 -> DMA-0 net_lat: 7
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Directory-0 Network Latencies
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Directory-0 -> L1Cache-0 net_lat: 7
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Directory-0 -> DMA-0 net_lat: 7
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DMA-0 Network Latencies
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DMA-0 -> L1Cache-0 net_lat: 7
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DMA-0 -> Directory-0 net_lat: 7
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--- End Topology Print ---
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Jul/06/2009 11:11:44
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Virtual_time_in_seconds: 0.87
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Virtual_time_in_minutes: 0.0145
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Virtual_time_in_hours: 0.000241667
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Virtual_time_in_days: 0.000241667
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Ruby_current_time: 26617001
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Ruby_start_time: 1
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Ruby_cycles: 26617000
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mbytes_resident: 145.273
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mbytes_total: 1330.63
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resident_ratio: 0.109179
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Total_misses: 0
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total_misses: 0 [ 0 ]
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user_misses: 0 [ 0 ]
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supervisor_misses: 0 [ 0 ]
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instruction_executed: 1 [ 1 ]
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ruby_cycles_executed: 26617001 [ 26617001 ]
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cycles_per_instruction: 2.6617e+07 [ 2.6617e+07 ]
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misses_per_thousand_instructions: 0 [ 0 ]
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transactions_started: 0 [ 0 ]
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transactions_ended: 0 [ 0 ]
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instructions_per_transaction: 0 [ 0 ]
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cycles_per_transaction: 0 [ 0 ]
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misses_per_transaction: 0 [ 0 ]
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L1D_cache cache stats:
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L1D_cache_total_misses: 0
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L1D_cache_total_demand_misses: 0
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L1D_cache_total_prefetches: 0
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L1D_cache_total_sw_prefetches: 0
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L1D_cache_total_hw_prefetches: 0
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L1D_cache_misses_per_transaction: 0
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L1D_cache_misses_per_instruction: 0
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L1D_cache_instructions_per_misses: NaN
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L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L1I_cache cache stats:
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L1I_cache_total_misses: 0
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L1I_cache_total_demand_misses: 0
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L1I_cache_total_prefetches: 0
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L1I_cache_total_sw_prefetches: 0
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L1I_cache_total_hw_prefetches: 0
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L1I_cache_misses_per_transaction: 0
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L1I_cache_misses_per_instruction: 0
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L1I_cache_instructions_per_misses: NaN
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L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L2_cache cache stats:
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L2_cache_total_misses: 0
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L2_cache_total_demand_misses: 0
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L2_cache_total_prefetches: 0
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L2_cache_total_sw_prefetches: 0
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L2_cache_total_hw_prefetches: 0
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L2_cache_misses_per_transaction: 0
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L2_cache_misses_per_instruction: 0
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L2_cache_instructions_per_misses: NaN
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L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Memory control:
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memory_total_requests: 1082
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memory_reads: 557
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memory_writes: 525
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memory_refreshes: 10431
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memory_total_request_delays: 1311
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memory_delays_per_request: 1.21165
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memory_delays_in_input_queue: 525
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memory_delays_behind_head_of_bank_queue: 0
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memory_delays_stalled_at_head_of_bank_queue: 786
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memory_stalls_for_bank_busy: 180
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memory_stalls_for_random_busy: 0
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memory_stalls_for_anti_starvation: 0
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memory_stalls_for_arbitration: 38
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memory_stalls_for_bus: 546
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memory_stalls_for_tfaw: 0
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memory_stalls_for_read_write_turnaround: 22
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memory_stalls_for_read_read_turnaround: 0
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accesses_per_bank: 58 43 53 51 67 43 40 32 18 19 34 51 41 46 28 10 31 8 8 12 42 34 9 20 10 25 44 26 25 58 55 41
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Busy Controller Counts:
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L1Cache-0:0
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Directory-0:0
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DMA-0:0
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Busy Bank Count:0
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L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L2TBE_usage: [binsize: 1 max: 1 count: 1082 average: 0.485213 | standard deviation: 0.500693 | 557 525 ]
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StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average: 1 | standard deviation: 0 | 0 8873 ]
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store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 2 max: 279 count: 8873 average: 12.5938 | standard deviation: 41.1326 | 0 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_1: [binsize: 2 max: 279 count: 6886 average: 9.86669 | standard deviation: 35.7801 | 0 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_2: [binsize: 2 max: 279 count: 1053 average: 24.4786 | standard deviation: 57.8541 | 0 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_3: [binsize: 2 max: 259 count: 934 average: 19.3009 | standard deviation: 51.067 | 0 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Request vs. RubySystem State Profile
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--------------------------------
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filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Message Delayed Cycles
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----------------------
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Total_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ]
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Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ]
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virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 557 average: 0 | standard deviation: 0 | 557 ]
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virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 525 average: 0 | standard deviation: 0 | 525 ]
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virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Resource Usage
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--------------
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 37883
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 48
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Network Stats
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-------------
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switch_0_inlinks: 2
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switch_0_outlinks: 2
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links_utilized_percent_switch_0: 0.000127033
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links_utilized_percent_switch_0_link_0: 5.08134e-05 bw: 640000 base_latency: 1
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links_utilized_percent_switch_0_link_1: 0.000203254 bw: 160000 base_latency: 1
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outgoing_messages_switch_0_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_0_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
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switch_1_inlinks: 2
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switch_1_outlinks: 2
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links_utilized_percent_switch_1: 0.000127033
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links_utilized_percent_switch_1_link_0: 5.08134e-05 bw: 640000 base_latency: 1
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links_utilized_percent_switch_1_link_1: 0.000203254 bw: 160000 base_latency: 1
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outgoing_messages_switch_1_link_0_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_0_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_1_link_1_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
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switch_2_inlinks: 2
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switch_2_outlinks: 2
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links_utilized_percent_switch_2: 0
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links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
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links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
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switch_3_inlinks: 3
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switch_3_outlinks: 3
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links_utilized_percent_switch_3: 0.000135502
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links_utilized_percent_switch_3_link_0: 0.000203254 bw: 160000 base_latency: 1
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links_utilized_percent_switch_3_link_1: 0.000203254 bw: 160000 base_latency: 1
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links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
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outgoing_messages_switch_3_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
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outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
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--- DMA ---
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- Event Counts -
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ReadRequest 0
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WriteRequest 0
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Data 0
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Ack 0
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- Transitions -
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READY ReadRequest 0 <--
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READY WriteRequest 0 <--
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BUSY_RD Data 0 <--
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BUSY_WR Ack 0 <--
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--- Directory ---
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- Event Counts -
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GETX 557
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GETS 0
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PUTX 525
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PUTX_NotOwner 0
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DMA_READ 0
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DMA_WRITE 0
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Memory_Data 557
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Memory_Ack 525
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- Transitions -
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I GETX 557
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I PUTX_NotOwner 0 <--
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I DMA_READ 0 <--
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I DMA_WRITE 0 <--
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M GETX 0 <--
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M PUTX 525
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M PUTX_NotOwner 0 <--
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M DMA_READ 0 <--
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M DMA_WRITE 0 <--
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M_DRD GETX 0 <--
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M_DRD PUTX 0 <--
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M_DWR GETX 0 <--
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M_DWR PUTX 0 <--
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M_DWRI Memory_Ack 0 <--
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IM GETX 0 <--
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IM GETS 0 <--
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IM PUTX 0 <--
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IM PUTX_NotOwner 0 <--
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IM DMA_READ 0 <--
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IM DMA_WRITE 0 <--
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IM Memory_Data 557
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MI GETX 0 <--
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MI GETS 0 <--
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MI PUTX 0 <--
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MI PUTX_NotOwner 0 <--
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MI DMA_READ 0 <--
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MI DMA_WRITE 0 <--
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MI Memory_Ack 525
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ID GETX 0 <--
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ID GETS 0 <--
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ID PUTX 0 <--
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ID PUTX_NotOwner 0 <--
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ID DMA_READ 0 <--
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ID DMA_WRITE 0 <--
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ID Memory_Data 0 <--
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ID_W GETX 0 <--
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ID_W GETS 0 <--
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ID_W PUTX 0 <--
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ID_W PUTX_NotOwner 0 <--
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ID_W DMA_READ 0 <--
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ID_W DMA_WRITE 0 <--
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ID_W Memory_Ack 0 <--
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--- L1Cache ---
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- Event Counts -
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Load 1053
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Ifetch 6886
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Store 934
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Data 557
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Fwd_GETX 0
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Inv 0
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Replacement 525
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Writeback_Ack 525
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Writeback_Nack 0
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- Transitions -
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I Load 140
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I Ifetch 320
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I Store 97
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I Inv 0 <--
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I Replacement 0 <--
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II Writeback_Nack 0 <--
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M Load 913
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M Ifetch 6566
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M Store 837
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M Fwd_GETX 0 <--
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M Inv 0 <--
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M Replacement 525
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MI Fwd_GETX 0 <--
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MI Inv 0 <--
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MI Writeback_Ack 525
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IS Data 460
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IM Data 97
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