681 lines
27 KiB
C++
681 lines
27 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers.
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*/
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#include "base/bitfield.hh"
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namespace iGbReg {
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// Registers used by the Intel GbE NIC
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const uint32_t REG_CTRL = 0x00000;
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const uint32_t REG_STATUS = 0x00008;
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const uint32_t REG_EECD = 0x00010;
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const uint32_t REG_EERD = 0x00014;
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const uint32_t REG_CTRL_EXT = 0x00018;
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const uint32_t REG_MDIC = 0x00020;
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const uint32_t REG_FCAL = 0x00028;
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const uint32_t REG_FCAH = 0x0002C;
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const uint32_t REG_FCT = 0x00030;
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const uint32_t REG_VET = 0x00038;
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const uint32_t REG_PBA = 0x01000;
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const uint32_t REG_ICR = 0x000C0;
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const uint32_t REG_ITR = 0x000C4;
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const uint32_t REG_ICS = 0x000C8;
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const uint32_t REG_IMS = 0x000D0;
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const uint32_t REG_IMC = 0x000D8;
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const uint32_t REG_IAM = 0x000E0;
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const uint32_t REG_RCTL = 0x00100;
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const uint32_t REG_FCTTV = 0x00170;
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const uint32_t REG_TIPG = 0x00410;
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const uint32_t REG_AIFS = 0x00458;
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const uint32_t REG_LEDCTL = 0x00e00;
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const uint32_t REG_FCRTL = 0x02160;
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const uint32_t REG_FCRTH = 0x02168;
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const uint32_t REG_RDBAL = 0x02800;
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const uint32_t REG_RDBAH = 0x02804;
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const uint32_t REG_RDLEN = 0x02808;
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const uint32_t REG_RDH = 0x02810;
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const uint32_t REG_RDT = 0x02818;
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const uint32_t REG_RDTR = 0x02820;
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const uint32_t REG_RXDCTL = 0x02828;
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const uint32_t REG_RADV = 0x0282C;
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const uint32_t REG_TCTL = 0x00400;
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const uint32_t REG_TDBAL = 0x03800;
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const uint32_t REG_TDBAH = 0x03804;
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const uint32_t REG_TDLEN = 0x03808;
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const uint32_t REG_TDH = 0x03810;
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const uint32_t REG_TDT = 0x03818;
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const uint32_t REG_TIDV = 0x03820;
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const uint32_t REG_TXDCTL = 0x03828;
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const uint32_t REG_TADV = 0x0382C;
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const uint32_t REG_CRCERRS = 0x04000;
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const uint32_t REG_RXCSUM = 0x05000;
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const uint32_t REG_MTA = 0x05200;
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const uint32_t REG_RAL = 0x05400;
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const uint32_t REG_RAH = 0x05404;
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const uint32_t REG_VFTA = 0x05600;
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const uint32_t REG_WUC = 0x05800;
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const uint32_t REG_MANC = 0x05820;
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const uint8_t EEPROM_READ_OPCODE_SPI = 0x03;
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const uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05;
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const uint8_t EEPROM_SIZE = 64;
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const uint16_t EEPROM_CSUM = 0xBABA;
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const uint8_t VLAN_FILTER_TABLE_SIZE = 128;
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const uint8_t RCV_ADDRESS_TABLE_SIZE = 16;
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const uint8_t MULTICAST_TABLE_SIZE = 128;
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const uint32_t STATS_REGS_SIZE = 0x124;
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// Registers in that are accessed in the PHY
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const uint8_t PHY_PSTATUS = 0x1;
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const uint8_t PHY_PID = 0x2;
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const uint8_t PHY_EPID = 0x3;
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const uint8_t PHY_GSTATUS = 10;
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const uint8_t PHY_EPSTATUS = 15;
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const uint8_t PHY_AGC = 18;
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// Receive Descriptor Status Flags
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const uint8_t RXDS_PIF = 0x80;
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const uint8_t RXDS_IPCS = 0x40;
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const uint8_t RXDS_TCPCS = 0x20;
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const uint8_t RXDS_UDPCS = 0x10;
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const uint8_t RXDS_VP = 0x08;
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const uint8_t RXDS_IXSM = 0x04;
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const uint8_t RXDS_EOP = 0x02;
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const uint8_t RXDS_DD = 0x01;
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// Receive Descriptor Error Flags
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const uint8_t RXDE_RXE = 0x80;
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const uint8_t RXDE_IPE = 0x40;
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const uint8_t RXDE_TCPE = 0x20;
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const uint8_t RXDE_SEQ = 0x04;
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const uint8_t RXDE_SE = 0x02;
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const uint8_t RXDE_CE = 0x01;
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// Interrupt types
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enum IntTypes
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{
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IT_NONE = 0x00000, //dummy value
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IT_TXDW = 0x00001,
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IT_TXQE = 0x00002,
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IT_LSC = 0x00004,
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IT_RXSEQ = 0x00008,
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IT_RXDMT = 0x00010,
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IT_RXO = 0x00040,
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IT_RXT = 0x00080,
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IT_MADC = 0x00200,
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IT_RXCFG = 0x00400,
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IT_GPI0 = 0x02000,
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IT_GPI1 = 0x04000,
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IT_TXDLOW = 0x08000,
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IT_SRPD = 0x10000,
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IT_ACK = 0x20000
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};
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// Receive Descriptor struct
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struct RxDesc {
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Addr buf;
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uint16_t len;
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uint16_t csum;
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uint8_t status;
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uint8_t errors;
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uint16_t vlan;
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};
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struct TxDesc {
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uint64_t d1;
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uint64_t d2;
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};
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namespace TxdOp {
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const uint8_t TXD_CNXT = 0x0;
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const uint8_t TXD_DATA = 0x1;
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bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); }
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uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); }
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bool isContext(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_CNXT; }
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bool isData(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_DATA; }
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Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; }
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Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); }
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void setDd(TxDesc *d)
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{
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replaceBits(d->d2, 35, 32, ULL(1));
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}
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bool ide(TxDesc *d) { return bits(d->d2, 31,31); }
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bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); }
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bool rs(TxDesc *d) { return bits(d->d2, 27,27); }
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bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); }
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bool tse(TxDesc *d) { return (isData(d) || isContext(d)) && bits(d->d2, 26,26); }
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bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); }
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bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); }
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bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); }
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bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); }
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uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); }
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uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); }
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bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); }
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bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); }
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int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); }
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int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); }
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int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); }
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int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); }
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int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); }
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int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); }
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int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); }
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int hdrlen(TxDesc *d) { assert(isContext(d)); return bits(d->d2,47,40); }
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} // namespace TxdOp
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#define ADD_FIELD32(NAME, OFFSET, BITS) \
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inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
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#define ADD_FIELD64(NAME, OFFSET, BITS) \
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inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
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struct Regs {
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template<class T>
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struct Reg {
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T _data;
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T operator()() { return _data; }
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const Reg<T> &operator=(T d) { _data = d; return *this;}
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bool operator==(T d) { return d == _data; }
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void operator()(T d) { _data = d; }
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Reg() { _data = 0; }
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void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(_data);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(_data);
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}
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};
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struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(fd,0,1); // full duplex
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ADD_FIELD32(bem,1,1); // big endian mode
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ADD_FIELD32(pcipr,2,1); // PCI priority
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ADD_FIELD32(lrst,3,1); // link reset
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ADD_FIELD32(tme,4,1); // test mode enable
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ADD_FIELD32(asde,5,1); // Auto-speed detection
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ADD_FIELD32(slu,6,1); // Set link up
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ADD_FIELD32(ilos,7,1); // invert los-of-signal
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ADD_FIELD32(speed,8,2); // speed selection bits
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ADD_FIELD32(be32,10,1); // big endian mode 32
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ADD_FIELD32(frcspd,11,1); // force speed
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ADD_FIELD32(frcdpx,12,1); // force duplex
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ADD_FIELD32(duden,13,1); // dock/undock enable
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ADD_FIELD32(dudpol,14,1); // dock/undock polarity
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ADD_FIELD32(fphyrst,15,1); // force phy reset
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ADD_FIELD32(extlen,16,1); // external link status enable
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ADD_FIELD32(rsvd,17,1); // reserved
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ADD_FIELD32(sdp0d,18,1); // software controlled pin data
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ADD_FIELD32(sdp1d,19,1); // software controlled pin data
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ADD_FIELD32(sdp2d,20,1); // software controlled pin data
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ADD_FIELD32(sdp3d,21,1); // software controlled pin data
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ADD_FIELD32(sdp0i,22,1); // software controlled pin dir
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ADD_FIELD32(sdp1i,23,1); // software controlled pin dir
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ADD_FIELD32(sdp2i,24,1); // software controlled pin dir
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ADD_FIELD32(sdp3i,25,1); // software controlled pin dir
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ADD_FIELD32(rst,26,1); // reset
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ADD_FIELD32(rfce,27,1); // receive flow control enable
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ADD_FIELD32(tfce,28,1); // transmit flow control enable
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ADD_FIELD32(rte,29,1); // routing tag enable
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ADD_FIELD32(vme,30,1); // vlan enable
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ADD_FIELD32(phyrst,31,1); // phy reset
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};
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CTRL ctrl;
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struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(fd,0,1); // full duplex
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ADD_FIELD32(lu,1,1); // link up
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ADD_FIELD32(func,2,2); // function id
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ADD_FIELD32(txoff,4,1); // transmission paused
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ADD_FIELD32(tbimode,5,1); // tbi mode
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ADD_FIELD32(speed,6,2); // link speed
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ADD_FIELD32(asdv,8,2); // auto speed detection value
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ADD_FIELD32(mtxckok,10,1); // mtx clock running ok
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ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot
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ADD_FIELD32(bus64,12,1); // in 64 bit slot
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ADD_FIELD32(pcix,13,1); // Pci mode
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ADD_FIELD32(pcixspd,14,2); // pci x speed
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};
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STATUS sts;
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struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(sk,0,1); // clack input to the eeprom
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ADD_FIELD32(cs,1,1); // chip select to eeprom
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ADD_FIELD32(din,2,1); // data input to eeprom
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ADD_FIELD32(dout,3,1); // data output bit
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ADD_FIELD32(fwe,4,2); // flash write enable
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ADD_FIELD32(ee_req,6,1); // request eeprom access
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ADD_FIELD32(ee_gnt,7,1); // grant eeprom access
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ADD_FIELD32(ee_pres,8,1); // eeprom present
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ADD_FIELD32(ee_size,9,1); // eeprom size
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ADD_FIELD32(ee_sz1,10,1); // eeprom size
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ADD_FIELD32(rsvd,11,2); // reserved
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ADD_FIELD32(ee_type,13,1); // type of eeprom
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} ;
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EECD eecd;
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struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(start,0,1); // start read
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ADD_FIELD32(done,4,1); // done read
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ADD_FIELD32(addr,8,8); // address
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ADD_FIELD32(data,16,16); // data
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};
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EERD eerd;
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struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio
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ADD_FIELD32(phyint,5,1); // reads the phy internal int status
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ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp
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ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp
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ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2
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ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2
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ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection
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ADD_FIELD32(eerst,13,1); // reset the eeprom
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ADD_FIELD32(spd_byps,15,1); // bypass speed select
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ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering
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ADD_FIELD32(vreg,21,1); // power down the voltage regulator
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ADD_FIELD32(link_mode,22,2); // interface to talk to the link
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ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ??
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ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device
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ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ??
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};
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CTRL_EXT ctrl_ext;
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struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(data,0,16); // data
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ADD_FIELD32(regadd,16,5); // register address
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ADD_FIELD32(phyadd,21,5); // phy addresses
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ADD_FIELD32(op,26,2); // opcode
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ADD_FIELD32(r,28,1); // ready
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ADD_FIELD32(i,29,1); // interrupt
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ADD_FIELD32(e,30,1); // error
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};
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MDIC mdic;
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struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(txdw,0,1) // tx descr witten back
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ADD_FIELD32(txqe,1,1) // tx queue empty
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ADD_FIELD32(lsc,2,1) // link status change
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ADD_FIELD32(rxseq,3,1) // rcv sequence error
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ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh
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ADD_FIELD32(rsvd1,5,1) // reserved
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ADD_FIELD32(rxo,6,1) // receive overrunn
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ADD_FIELD32(rxt0,7,1) // receiver timer interrupt
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ADD_FIELD32(mdac,9,1) // mdi/o access complete
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ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets
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ADD_FIELD32(phyint,12,1) // phy interrupt
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ADD_FIELD32(gpi1,13,1) // gpi int 1
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ADD_FIELD32(gpi2,14,1) // gpi int 2
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ADD_FIELD32(txdlow,15,1) // transmit desc low thresh
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ADD_FIELD32(srpd,16,1) // small receive packet detected
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ADD_FIELD32(ack,17,1); // receive ack frame
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ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt
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};
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ICR icr;
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uint32_t imr; // register that contains the current interrupt mask
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struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval
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// specified in 256ns interrupts
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};
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ITR itr;
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// When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write
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// causes the IAM register contents to be written into the IMC
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// automatically clearing all interrupts that have a bit in the IAM set
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uint32_t iam;
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struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register
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using Reg<uint32_t>::operator=;
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ADD_FIELD32(rst,0,1); // Reset
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ADD_FIELD32(en,1,1); // Enable
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ADD_FIELD32(sbp,2,1); // Store bad packets
|
|
ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled
|
|
ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled
|
|
ADD_FIELD32(lpe,5,1); // long packet reception enabled
|
|
ADD_FIELD32(lbm,6,2); //
|
|
ADD_FIELD32(rdmts,8,2); //
|
|
ADD_FIELD32(mo,12,2); //
|
|
ADD_FIELD32(mdr,14,1); //
|
|
ADD_FIELD32(bam,15,1); //
|
|
ADD_FIELD32(bsize,16,2); //
|
|
ADD_FIELD32(vfe,18,1); //
|
|
ADD_FIELD32(cfien,19,1); //
|
|
ADD_FIELD32(cfi,20,1); //
|
|
ADD_FIELD32(dpf,22,1); // discard pause frames
|
|
ADD_FIELD32(pmcf,23,1); // pass mac control frames
|
|
ADD_FIELD32(bsex,25,1); // buffer size extension
|
|
ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet
|
|
int descSize()
|
|
{
|
|
switch(bsize()) {
|
|
case 0: return bsex() == 0 ? 2048 : -1;
|
|
case 1: return bsex() == 0 ? 1024 : 16384;
|
|
case 2: return bsex() == 0 ? 512 : 8192;
|
|
case 3: return bsex() == 0 ? 256 : 4096;
|
|
default:
|
|
return -1;
|
|
}
|
|
}
|
|
};
|
|
RCTL rctl;
|
|
|
|
struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(ttv,0,16); // Transmit Timer Value
|
|
};
|
|
FCTTV fcttv;
|
|
|
|
struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(rst,0,1); // Reset
|
|
ADD_FIELD32(en,1,1); // Enable
|
|
ADD_FIELD32(bce,2,1); // busy check enable
|
|
ADD_FIELD32(psp,3,1); // pad short packets
|
|
ADD_FIELD32(ct,4,8); // collision threshold
|
|
ADD_FIELD32(cold,12,10); // collision distance
|
|
ADD_FIELD32(swxoff,22,1); // software xoff transmission
|
|
ADD_FIELD32(pbe,23,1); // packet burst enable
|
|
ADD_FIELD32(rtlc,24,1); // retransmit late collisions
|
|
ADD_FIELD32(nrtu,25,1); // on underrun no TX
|
|
ADD_FIELD32(mulr,26,1); // multiple request
|
|
};
|
|
TCTL tctl;
|
|
|
|
struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(rxa,0,16);
|
|
ADD_FIELD32(txa,16,16);
|
|
};
|
|
PBA pba;
|
|
|
|
struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have
|
|
// a larger buffer
|
|
ADD_FIELD32(xone, 31,1);
|
|
};
|
|
FCRTL fcrtl;
|
|
|
|
struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have
|
|
//a larger buffer
|
|
ADD_FIELD32(xfce, 31,1);
|
|
};
|
|
FCRTH fcrth;
|
|
|
|
struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register
|
|
using Reg<uint64_t>::operator=;
|
|
ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring
|
|
ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring
|
|
};
|
|
RDBA rdba;
|
|
|
|
struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
|
|
};
|
|
RDLEN rdlen;
|
|
|
|
struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(rdh,0,16); // head of the descriptor ring
|
|
};
|
|
RDH rdh;
|
|
|
|
struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(rdt,0,16); // tail of the descriptor ring
|
|
};
|
|
RDT rdt;
|
|
|
|
struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(delay,0,16); // receive delay timer
|
|
ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ??
|
|
};
|
|
RDTR rdtr;
|
|
|
|
struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this
|
|
// consider prefetch
|
|
ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to
|
|
// consider prefetch
|
|
ADD_FIELD32(wthresh,16,6); // writeback threshold
|
|
ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline
|
|
};
|
|
RXDCTL rxdctl;
|
|
|
|
struct RADV : public Reg<uint32_t> { // 0x282C RADV Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(idv,0,16); // absolute interrupt delay
|
|
};
|
|
RADV radv;
|
|
|
|
struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(idv,0,12); // size to interrutp on small packets
|
|
};
|
|
RSRPD rsrpd;
|
|
|
|
struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register
|
|
using Reg<uint64_t>::operator=;
|
|
ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring
|
|
ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring
|
|
};
|
|
TDBA tdba;
|
|
|
|
struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer
|
|
};
|
|
TDLEN tdlen;
|
|
|
|
struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(tdh,0,16); // head of the descriptor ring
|
|
};
|
|
TDH tdh;
|
|
|
|
struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(tdt,0,16); // tail of the descriptor ring
|
|
};
|
|
TDT tdt;
|
|
|
|
struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(idv,0,16); // interrupt delay
|
|
};
|
|
TIDV tidv;
|
|
|
|
struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is
|
|
// below this number, a prefetch is considered
|
|
ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory
|
|
// before a prefetch is considered
|
|
ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until
|
|
// writeback is considered
|
|
ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline,
|
|
// 1 == desscriptor)
|
|
ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt
|
|
// below this level
|
|
};
|
|
TXDCTL txdctl;
|
|
|
|
struct TADV : public Reg<uint32_t> { // 0x382C TADV Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(idv,0,16); // absolute interrupt delay
|
|
};
|
|
TADV tadv;
|
|
|
|
struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(pcss,0,8);
|
|
ADD_FIELD32(ipofld,8,1);
|
|
ADD_FIELD32(tuofld,9,1);
|
|
};
|
|
RXCSUM rxcsum;
|
|
|
|
struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register
|
|
using Reg<uint32_t>::operator=;
|
|
ADD_FIELD32(smbus,0,1); // SMBus enabled #####
|
|
ADD_FIELD32(asf,1,1); // ASF enabled #####
|
|
ADD_FIELD32(ronforce,2,1); // reset of force
|
|
ADD_FIELD32(rsvd,3,5); // reserved
|
|
ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering
|
|
ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering
|
|
ADD_FIELD32(ipv4,10,1); // enable ipv4
|
|
ADD_FIELD32(ipv6,11,1); // enable ipv6
|
|
ADD_FIELD32(snap,12,1); // accept snap
|
|
ADD_FIELD32(arp,13,1); // filter arp #####
|
|
ADD_FIELD32(neighbor,14,1); // neighbor discovery
|
|
ADD_FIELD32(arp_resp,15,1); // arp response
|
|
ADD_FIELD32(tcorst,16,1); // tco reset happened
|
|
ADD_FIELD32(rcvtco,17,1); // receive tco enabled ######
|
|
ADD_FIELD32(blkphyrst,18,1);// block phy resets ########
|
|
ADD_FIELD32(rcvall,19,1); // receive all
|
|
ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ######
|
|
ADD_FIELD32(mng2host,21,1); // mng2 host packets #######
|
|
ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering
|
|
ADD_FIELD32(xsumfilter,23,1); // checksum filtering
|
|
ADD_FIELD32(brfilter,24,1); // broadcast filtering
|
|
ADD_FIELD32(smbreq,25,1); // smb request
|
|
ADD_FIELD32(smbgnt,26,1); // smb grant
|
|
ADD_FIELD32(smbclkin,27,1); // smbclkin
|
|
ADD_FIELD32(smbdatain,28,1); // smbdatain
|
|
ADD_FIELD32(smbdataout,29,1); // smb data out
|
|
ADD_FIELD32(smbclkout,30,1); // smb clock out
|
|
};
|
|
MANC manc;
|
|
|
|
void serialize(std::ostream &os)
|
|
{
|
|
paramOut(os, "ctrl", ctrl._data);
|
|
paramOut(os, "sts", sts._data);
|
|
paramOut(os, "eecd", eecd._data);
|
|
paramOut(os, "eerd", eerd._data);
|
|
paramOut(os, "ctrl_ext", ctrl_ext._data);
|
|
paramOut(os, "mdic", mdic._data);
|
|
paramOut(os, "icr", icr._data);
|
|
SERIALIZE_SCALAR(imr);
|
|
paramOut(os, "itr", itr._data);
|
|
SERIALIZE_SCALAR(iam);
|
|
paramOut(os, "rctl", rctl._data);
|
|
paramOut(os, "fcttv", fcttv._data);
|
|
paramOut(os, "tctl", tctl._data);
|
|
paramOut(os, "pba", pba._data);
|
|
paramOut(os, "fcrtl", fcrtl._data);
|
|
paramOut(os, "fcrth", fcrth._data);
|
|
paramOut(os, "rdba", rdba._data);
|
|
paramOut(os, "rdlen", rdlen._data);
|
|
paramOut(os, "rdh", rdh._data);
|
|
paramOut(os, "rdt", rdt._data);
|
|
paramOut(os, "rdtr", rdtr._data);
|
|
paramOut(os, "rxdctl", rxdctl._data);
|
|
paramOut(os, "radv", radv._data);
|
|
paramOut(os, "rsrpd", rsrpd._data);
|
|
paramOut(os, "tdba", tdba._data);
|
|
paramOut(os, "tdlen", tdlen._data);
|
|
paramOut(os, "tdh", tdh._data);
|
|
paramOut(os, "tdt", tdt._data);
|
|
paramOut(os, "tidv", tidv._data);
|
|
paramOut(os, "txdctl", txdctl._data);
|
|
paramOut(os, "tadv", tadv._data);
|
|
paramOut(os, "rxcsum", rxcsum._data);
|
|
paramOut(os, "manc", manc._data);
|
|
}
|
|
|
|
void unserialize(Checkpoint *cp, const std::string §ion)
|
|
{
|
|
paramIn(cp, section, "ctrl", ctrl._data);
|
|
paramIn(cp, section, "sts", sts._data);
|
|
paramIn(cp, section, "eecd", eecd._data);
|
|
paramIn(cp, section, "eerd", eerd._data);
|
|
paramIn(cp, section, "ctrl_ext", ctrl_ext._data);
|
|
paramIn(cp, section, "mdic", mdic._data);
|
|
paramIn(cp, section, "icr", icr._data);
|
|
UNSERIALIZE_SCALAR(imr);
|
|
paramIn(cp, section, "itr", itr._data);
|
|
UNSERIALIZE_SCALAR(iam);
|
|
paramIn(cp, section, "rctl", rctl._data);
|
|
paramIn(cp, section, "fcttv", fcttv._data);
|
|
paramIn(cp, section, "tctl", tctl._data);
|
|
paramIn(cp, section, "pba", pba._data);
|
|
paramIn(cp, section, "fcrtl", fcrtl._data);
|
|
paramIn(cp, section, "fcrth", fcrth._data);
|
|
paramIn(cp, section, "rdba", rdba._data);
|
|
paramIn(cp, section, "rdlen", rdlen._data);
|
|
paramIn(cp, section, "rdh", rdh._data);
|
|
paramIn(cp, section, "rdt", rdt._data);
|
|
paramIn(cp, section, "rdtr", rdtr._data);
|
|
paramIn(cp, section, "rxdctl", rxdctl._data);
|
|
paramIn(cp, section, "radv", radv._data);
|
|
paramIn(cp, section, "rsrpd", rsrpd._data);
|
|
paramIn(cp, section, "tdba", tdba._data);
|
|
paramIn(cp, section, "tdlen", tdlen._data);
|
|
paramIn(cp, section, "tdh", tdh._data);
|
|
paramIn(cp, section, "tdt", tdt._data);
|
|
paramIn(cp, section, "tidv", tidv._data);
|
|
paramIn(cp, section, "txdctl", txdctl._data);
|
|
paramIn(cp, section, "tadv", tadv._data);
|
|
paramIn(cp, section, "rxcsum", rxcsum._data);
|
|
paramIn(cp, section, "manc", manc._data);
|
|
}
|
|
};
|
|
} // iGbReg namespace
|