413 lines
15 KiB
Text
413 lines
15 KiB
Text
// Copyright (c) 2007 The Hewlett-Packard Development Company
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// All rights reserved.
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//
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// Redistribution and use of this software in source and binary forms,
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// with or without modification, are permitted provided that the
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// following conditions are met:
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//
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// The software must be used only for Non-Commercial Use which means any
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// use which is NOT directed to receiving any direct monetary
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// compensation for, or commercial advantage from such use. Illustrative
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// examples of non-commercial use are academic research, personal study,
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// teaching, education and corporate research & development.
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// Illustrative examples of commercial use are distributing products for
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// commercial advantage and providing services using the software for
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// commercial advantage.
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//
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// If you wish to use this software or functionality therein that may be
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// covered by patents for commercial use, please contact:
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// Director of Intellectual Property Licensing
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// Office of Strategy and Technology
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// Hewlett-Packard Company
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// 1501 Page Mill Road
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// Palo Alto, California 94304
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer. Redistributions
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// in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or
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// other materials provided with the distribution. Neither the name of
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// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission. No right of
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// sublicense is granted herewith. Derivatives of the software and
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// output created using the software may be prepared, but only for
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// Non-Commercial Uses. Derivatives of the software may be shared with
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// others provided: (i) the others agree to abide by the list of
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// conditions herein which includes the Non-Commercial Use restrictions;
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// and (ii) such Derivatives of the software include the above copyright
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// notice to acknowledge the contribution from this software where
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// applicable, this list of conditions and the disclaimer below.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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//////////////////////////////////////////////////////////////////////////
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//
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// RegOp Microop templates
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//
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//////////////////////////////////////////////////////////////////////////
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output header {{
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/**
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* Base classes for RegOps which provides a generateDisassembly method.
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*/
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class RegOp : public X86MicroopBase
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{
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protected:
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const RegIndex src1;
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const RegIndex src2;
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const RegIndex dest;
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const bool setStatus;
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const uint8_t dataSize;
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const uint8_t ext;
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// Constructor
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RegOp(ExtMachInst _machInst,
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const char *mnem, const char *_instMnem,
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bool isMicro, bool isDelayed,
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bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext,
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OpClass __opClass) :
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X86MicroopBase(_machInst, mnem, _instMnem,
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isMicro, isDelayed, isFirst, isLast,
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__opClass),
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src1(_src1), src2(_src2), dest(_dest),
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setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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class RegOpImm : public X86MicroopBase
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{
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protected:
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const RegIndex src1;
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const uint8_t imm8;
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const RegIndex dest;
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const bool setStatus;
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const uint8_t dataSize;
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const uint8_t ext;
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// Constructor
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RegOpImm(ExtMachInst _machInst,
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const char * mnem, const char *_instMnem,
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bool isMicro, bool isDelayed,
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bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext,
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OpClass __opClass) :
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X86MicroopBase(_machInst, mnem, _instMnem,
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isMicro, isDelayed, isFirst, isLast,
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__opClass),
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src1(_src1), imm8(_imm8), dest(_dest),
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setStatus(_setStatus), dataSize(_dataSize), ext(_ext)
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{
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}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string RegOp::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, instMnem, mnemonic);
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printReg(response, dest);
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response << ", ";
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printReg(response, src1);
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response << ", ";
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printReg(response, src2);
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return response.str();
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}
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std::string RegOpImm::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream response;
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printMnemonic(response, instMnem, mnemonic);
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printReg(response, dest);
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response << ", ";
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printReg(response, src1);
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ccprintf(response, ", %#x", imm8);
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return response.str();
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}
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}};
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def template MicroRegOpExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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//Write the resulting state to the execution context
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroRegOpImmExecute {{
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Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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//Write the resulting state to the execution context
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if(fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroRegOpDeclare {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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void buildMe();
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public:
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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%(class_name)s(ExtMachInst _machInst,
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const char * instMnem,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroRegOpImmDeclare {{
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class %(class_name)sImm : public %(base_class)s
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{
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protected:
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void buildMe();
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public:
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%(class_name)sImm(ExtMachInst _machInst,
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const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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%(class_name)sImm(ExtMachInst _machInst,
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const char * instMnem,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext);
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%(BasicExecDeclare)s
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};
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}};
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def template MicroRegOpConstructor {{
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inline void %(class_name)s::buildMe()
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{
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%(constructor)s;
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}
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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false, false, false, false,
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_src1, _src2, _dest, _setStatus, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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inline %(class_name)s::%(class_name)s(
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, RegIndex _src2, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _src2, _dest, _setStatus, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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}};
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def template MicroRegOpImmConstructor {{
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inline void %(class_name)sImm::buildMe()
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{
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%(constructor)s;
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}
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inline %(class_name)sImm::%(class_name)sImm(
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ExtMachInst machInst, const char * instMnem,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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false, false, false, false,
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_src1, _imm8, _dest, _setStatus, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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inline %(class_name)sImm::%(class_name)sImm(
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ExtMachInst machInst, const char * instMnem,
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bool isMicro, bool isDelayed, bool isFirst, bool isLast,
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RegIndex _src1, uint8_t _imm8, RegIndex _dest,
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bool _setStatus, uint8_t _dataSize, uint8_t _ext) :
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%(base_class)s(machInst, "%(mnemonic)s", instMnem,
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isMicro, isDelayed, isFirst, isLast,
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_src1, _imm8, _dest, _setStatus, _dataSize, _ext,
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%(op_class)s)
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{
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buildMe();
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}
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}};
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let {{
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class RegOp(X86Microop):
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def __init__(self, dest, src1, src2):
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self.dest = dest
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self.src1 = src1
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self.src2 = src2
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self.setStatus = False
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self.dataSize = "env.dataSize"
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self.ext = 0
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(src2)s, %(dest)s,
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%(setStatus)s, %(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "src2" : self.src2,
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"dest" : self.dest,
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"setStatus" : self.cppBool(self.setStatus),
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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class RegOpImm(X86Microop):
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def __init__(self, dest, src1, imm8):
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self.dest = dest
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self.src1 = src1
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self.imm8 = imm8
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self.setStatus = False
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self.dataSize = "env.dataSize"
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self.ext = 0
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def getAllocator(self, *microFlags):
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allocator = '''new %(class_name)s(machInst, mnemonic
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%(flags)s, %(src1)s, %(imm8)s, %(dest)s,
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%(setStatus)s, %(dataSize)s, %(ext)s)''' % {
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"class_name" : self.className,
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"flags" : self.microFlagsText(microFlags),
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"src1" : self.src1, "imm8" : self.imm8,
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"dest" : self.dest,
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"setStatus" : self.cppBool(self.setStatus),
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"dataSize" : self.dataSize,
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"ext" : self.ext}
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return allocator
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}};
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let {{
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# Make these empty strings so that concatenating onto
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# them will always work.
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header_output = ""
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decoder_output = ""
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exec_output = ""
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def defineMicroRegOp(mnemonic, code):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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Name = mnemonic
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name = mnemonic.lower()
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# Find op2 in each of the instruction definitions. Create two versions
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# of the code, one with an integer operand, and one with an immediate
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# operand.
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matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
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regCode = matcher.sub("SrcReg2", code)
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immCode = matcher.sub("imm8", code)
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# Build up the all register version of this micro op
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iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode})
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header_output += MicroRegOpDeclare.subst(iop)
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decoder_output += MicroRegOpConstructor.subst(iop)
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exec_output += MicroRegOpExecute.subst(iop)
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class RegOpChild(RegOp):
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def __init__(self, dest, src1, src2):
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super(RegOpChild, self).__init__(dest, src1, src2)
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self.className = Name
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self.mnemonic = name
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microopClasses[name] = RegOpChild
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# Build up the immediate version of this micro op
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iop = InstObjParams(name + "i", Name,
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'RegOpImm', {"code" : immCode})
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header_output += MicroRegOpImmDeclare.subst(iop)
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decoder_output += MicroRegOpImmConstructor.subst(iop)
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exec_output += MicroRegOpImmExecute.subst(iop)
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class RegOpImmChild(RegOpImm):
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def __init__(self, dest, src1, imm):
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super(RegOpImmChild, self).__init__(dest, src1, imm)
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self.className = Name + "Imm"
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self.mnemonic = name + "i"
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microopClasses[name + "i"] = RegOpImmChild
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
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defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
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defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
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defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
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defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
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defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
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}};
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