gem5/src/arch/sparc/isa
Gabe Black 6dddca9511 Add an integer microcode register.
--HG--
extra : convert_revision : f23dbfdfe44e8e6cdd6948000669ad4f743b9fb4
2006-10-29 01:58:37 -05:00
..
formats Fixed the priv instruction format. 2006-10-25 17:58:44 -04:00
base.isa Made sure the constructor for insts use ExtMachInst rather than MachInst, since otherwise the EXT_ASI field is lost. 2006-10-16 15:52:14 -04:00
bitfields.isa Fixed the bitfield FCN to include the right bits. 2006-10-25 17:50:39 -04:00
decoder.isa Got rid of some outdated comments. 2006-10-27 01:43:51 -04:00
includes.isa Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 2006-10-23 07:55:52 -04:00
main.isa Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 2006-10-23 07:55:52 -04:00
operands.isa Add an integer microcode register. 2006-10-29 01:58:37 -05:00