SConscript: compile ide devices base/chunk_generator.hh: add another parameter to the chuck generator called complete() which returns the number of bytes transfered so far. Very useful for adding to a pointer. configs/test/fs.py: Add ide disk to fs test configuration dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: update for new memory system mem/bus.cc: support devices that return multiple ranges remove old ranges before using new info mem/packet.hh: make senderstate void* per steve's request that we use every construct possible in C++ mem/physical.cc: have memory stamp the packet with the time. mem/physical.hh: actually set the memory latency variable python/m5/objects/Device.py: Add DmaDevice python/m5/objects/Ide.py: Ide disk no longer has a physmem pointer python/m5/objects/Pci.py: update pci device for newmem python/m5/objects/PhysicalMemory.py: add latency parameter for physical memory sim/byteswap.hh: use fast architecture dependent byteswap calls if they exist --HG-- extra : convert_revision : e3cf2e8f61064ad302d94bc22010a00c59f3f793
55 lines
2.4 KiB
Python
55 lines
2.4 KiB
Python
from m5 import *
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from Device import BasicPioDevice, DmaDevice
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class PciConfigData(SimObject):
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type = 'PciConfigData'
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VendorID = Param.UInt16("Vendor ID")
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DeviceID = Param.UInt16("Device ID")
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Command = Param.UInt16(0, "Command")
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Status = Param.UInt16(0, "Status")
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Revision = Param.UInt8(0, "Device")
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ProgIF = Param.UInt8(0, "Programming Interface")
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SubClassCode = Param.UInt8(0, "Sub-Class Code")
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ClassCode = Param.UInt8(0, "Class Code")
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CacheLineSize = Param.UInt8(0, "System Cacheline Size")
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LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
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HeaderType = Param.UInt8(0, "PCI Header Type")
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BIST = Param.UInt8(0, "Built In Self Test")
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BAR0 = Param.UInt32(0x00, "Base Address Register 0")
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BAR1 = Param.UInt32(0x00, "Base Address Register 1")
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BAR2 = Param.UInt32(0x00, "Base Address Register 2")
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BAR3 = Param.UInt32(0x00, "Base Address Register 3")
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BAR4 = Param.UInt32(0x00, "Base Address Register 4")
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BAR5 = Param.UInt32(0x00, "Base Address Register 5")
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BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
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BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
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BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
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BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
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BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
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BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
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ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
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InterruptLine = Param.UInt8(0x00, "Interrupt Line")
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InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
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MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
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MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
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class PciConfigAll(BasicPioDevice):
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type = 'PciConfigAll'
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class PciDevice(DmaDevice):
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type = 'PciDevice'
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abstract = True
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pci_bus = Param.Int("PCI bus")
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pci_dev = Param.Int("PCI device number")
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pci_func = Param.Int("PCI function code")
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pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
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configdata = Param.PciConfigData(Parent.any, "PCI Config data")
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configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
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class PciFake(PciDevice):
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type = 'PciFake'
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