gem5/src/cpu/simple
Ali Saidi 6d9d0c68b5 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
2007-01-26 18:50:28 -05:00
..
atomic.cc Modify ISA and staticInst to support a IsFirstMicroOp flag 2007-01-16 19:06:05 -05:00
atomic.hh little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem). 2006-12-15 17:55:47 -05:00
base.cc Merge zizzer:/bk/newmem 2007-01-26 12:51:24 -05:00
base.hh make our code a little more standards compliant 2007-01-26 18:48:51 -05:00
timing.cc Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. 2006-11-29 16:07:55 -05:00
timing.hh little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem). 2006-12-15 17:55:47 -05:00